Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO K.sub.DCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.

Methods and circuits are provided for range extension of a phase-locked loop (PLL). The PLL uses a phase subtractor with a limited unextended range. It also includes first and second registers and combinatorial logic. The phase subtractor calculates the current phase difference. The first register stores the previous phase difference. The combinatorial logic determines, from the current phase difference and the previous phase difference, if a range excursion occurs, and if it is upward or downward. When an upward excursion occurs, the value in the second register is incremented. When a downward excursion occurs, the value of the second register is decremented. The bits in the second register are combined with the bits of the current phase difference to obtain an extended current phase difference.

An electronic device including: a delay circuit configured to adjust a delay of an input for generating an output signal; and an input selection circuit coupled to the delay circuit, the input selection circuit configured to control a phase for a clock input based at least in part on a measurement of a delay corresponding to the delay circuit in generating the input.

Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.

The clock generator is provided and includes a phase detector, a voltage generator, a voltage-to-current converter, and an oscillation circuit. The voltage generator generates a control voltage. The voltage-to-current converter converts the control voltage into an internal current having a level based on a resistance value of a resistor circuit, the resistance value set based on first control information. The oscillation circuit generates a output clock having a frequency based on the level of the internal current and a capacitance value of a capacitor circuit, the capacitance value set based on second control information. The clock generator maintains a frequency value and varies jitter characteristics of the output clock in response to the first control information and the second control information.

A digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit is disclosed, which comprises: a DTC error compensator arranged to receive a phase offset signal being a processed output from a time-to-digital converter (TDC) circuit, the phase offset signal includes a DTC error corresponding to a phase difference between a reference clock signal processed by a DTC circuit and a feedback clock signal derived from an output signal of the ADPLL circuit. The compensator is arranged to process the phase offset signal for generating a digital signal representative of the DTC error, which is provided as an output signal. Also, the output signal is arranged to be subtracted from the phase offset signal to obtain a phase rectified signal of the phase offset signal.

A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequency signal. The transmitter circuit also includes a power amplifier configured to selectively drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal and the drive signal of the power amplifier. The programmable delay circuit is programmed such that a first value of a particular operational characteristic of the phase locked loop circuit is substantially equal to a second value of the operational characteristic of the phase locked loop circuit. The first value is measured with the power amplifier not driving the antenna. The second value is measured with the power amplifier driving the antenna.

An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.

Oscillator calibration circuits and wireless transmitters including oscillator calibration circuits. An oscillator calibration circuit includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC calibrates the frequency of the first oscillator using an over-the-air reference signal, wherein the first FLC calibrates the first oscillator prior to a data transmission session and remains free running during the data transmission session.

A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequency signal. The transmitter circuit also includes a power amplifier configured to selectively drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal and the drive signal of the power amplifier. The programmable delay circuit is programmed such that a first value of a particular operational characteristic of the phase locked loop circuit is substantially equal to a second value of the operational characteristic of the phase locked loop circuit. The first value is measured with the power amplifier not driving the antenna. The second value is measured with the power amplifier driving the antenna.