A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.

A data transmitting and receiving system includes a first device including an encoder configured to encode row data to generate precoding data and a transmitter configured to transmit the precoding data through a transmission channel and a second device including an integrator configured to perform an integral on the precoding data, an integral sampler including a plurality of samplers configured to output sampling data based on an offset value and an output value of the integrator, a decoder configured to decode outputs of some of the samplers to generate decoded data, and a phase detector configured to detect a phase difference between the precoding data and a clock based on the decoded data and an output of another one of the samplers.

One embodiment relates to a transmitting device, a receiving device, and the like for preventing increases in the number of communication links, power consumption, and circuit layout area. The transmitting device includes a high-speed signal generator, a low-speed signal generator, and a signal superimposing unit. The high-speed signal generator generates a high-speed signal having a limited frequency band. The low-speed signal generator generates a low-speed signal having a frequency lower than the frequency band of the high-speed signal. The signal superimposing unit outputs a superimposed signal of the high-speed signal and the low-speed signal. The receiving device includes a signal separator and a recovery unit. The signal separator separates the received signal into the high-speed signal and the low-speed signal. The recovery unit performs frequency tracking based on the separated low-speed signal and performs phase tracking based on the separated high-speed signal.

A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.

A clock data recovery circuit includes a phase detector, a first signal processing path, a second signal processing path, an oscillator circuit and a phase control circuit. The phase detector samples input data signal according to first clock signals to generate an up control signal and a down control signal. The first signal processing path includes at least one first signal processing device generating a phase control signal according to the up control signal and the down control signal. The second signal processing path includes at least one second signal processing device generating a frequency control signal according to the up control signal and the down control signal. The oscillator circuit generates second clock signals according to the frequency control signal. The phase control circuit controls phases of the second clock signals according to the phase control signal to generate the first clock signals.

Disclosed are a digital CDR circuit and a feedback loop circuit including the same. The digital CDR circuit includes a phase detector that receives an input signal and outputs a phase detection result signal corresponding to a determination result for a sampling time based on the input signal, a charge pump that receives the phase detection result signal and outputs an amplified signal obtained by multiplying the phase detection result signal by a gain, a loop filter that receives the amplified signal and filters the amplified signal to output a filtered signal, and a phase shift control code generator that generates a control signal for controlling a phase of a signal based on the filtered signal, and the input signal includes plural data signals and plural error signals, and the data signals and the error signals are digital signals which are quantized based on a signal magnitude.

In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.

A display driving device and an anti-interference method thereof are provided. A timing controller outputs a data signal. A source driver detects an interference event according to the data signal, and outputs a feedback signal to the timing controller in response to the detection result of the interference event. The timing controller adjusts the signal strength of the data signal according to the feedback signal.

Disclosed are a clock and data recovery circuit, method and apparatus. The circuit comprises a receiving module for receiving an analog signal; a first equalization module connected to the receiving module, the first equalization module comprising a first totalizer and a second totalizer; a first sampling module connected to an output end of the first totalizer, the first sampling module comprising a first edge sampler and a second edge sampler that are connected to the output end of the first totalizer, respectively; a second sampling module connected to an output end of the second totalizer; a data processing module connected to both the first sampling module and the second sampling module; a clock recovery module connected to the data processing module; and an output module connected to the clock recovery module. In the present application, by means of the manner, a phase can be adjusted using a bias voltage, thereby accurately recovering clock information.

Disclosed are some examples of Phase interpolator circuitry used in retimer systems. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track a plurality data packets. Phase interpolator circuitry is coupled with clock data recovery circuitry. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal.