A voltage controlled oscillator (VCO) in a frequency synthesizer generates an output signal having a target frequency by being coarse tuned in accordance with a channel code derived through a binary tree search. Thereafter, the output signal of the VCO may be further tuned using a phase lock loop (PLL) circuit. Each stage of the binary tree search includes a comparison step that determines a channel code bit, and another step that confirms that the channel code converges to a final channel code within an established stage range value.

A voltage controlled oscillator (VCO) in a frequency synthesizer generates an output signal having a target frequency by being coarse tuned in accordance with a channel code derived through a binary tree search. Thereafter, the output signal of the VCO may be further tuned using a phase lock loop (PLL) circuit. Each stage of the binary tree search includes a comparison step that determines a channel code bit, and another step that confirms that the channel code converges to a final channel code within an established stage range value.

A system includes a digital phase-locked loop (DPLL) having a loop filter and a digitally-controlled oscillator (DCO). The system also includes a clock generator coupled to an output of the DPLL, and a plurality of clock domains coupled to the clock generator. The DPLL is configured to transition between a low power mode and a normal mode, wherein the loop filter is configured to maintain its value when the DPLL transitions from the normal mode to the low power mode. The DCO is configured to output a DCO clock signal based on the maintained loop filter value when the DPLL transitions from the low power mode to the normal mode.

A system includes a digital phase-locked loop (DPLL) having a loop filter and a digitally-controlled oscillator (DCO). The system also includes a clock generator coupled to an output of the DPLL, and a plurality of clock domains coupled to the clock generator. The DPLL is configured to transition between a low power mode and a normal mode, wherein the loop filter is configured to maintain its value when the DPLL transitions from the normal mode to the low power mode. The DCO is configured to output a DCO clock signal based on the maintained loop filter value when the DPLL transitions from the low power mode to the normal mode.

A phase locked loop device may include: a frequency modulating circuit configured to output a reference signal obtained by multiplying a frequency of an input signal by a predetermined ratio based on the input signal; a sigma-delta modulator configured to output division ratio information on one of a plurality of division rates at a number of times proportional to a frequency of the reference signal; and a phase locked loop (PLL) circuit configured to determine whether to activate based on a command signal, and, when activated, perform a phase-locking operation based on a fractional division based on the reference signal and the division ratio information.

In a time-to-digital converter, a digital signal outputted by a phase information generator is inputted to each of the D terminals of first through Nth (N is a natural number equal to or greater than 2) D-type flip-flop circuits in a first flip-flop group, each of the D terminals is connected to one end of a first delay element, the C terminal of the first D-type flip-flop circuit is connected to another end of the first delay element, the other end of the first delay element is connected to an input terminal, and, when N, the number of flip-flop circuits in the first flip-flop group, is equal to or greater than 3, for each J a natural number from 2 to N−1, C terminal of the (J+1)th D-type flip-flop circuit is connected to one end of the Jth delay element and one end of the (J−1)th delay element is connected to the other end of the Jth delay element.

An integrated circuit (IC) chip including clock generation circuitry to generate a clock signal. Clock interface circuitry is coupled to the clock generation circuitry and includes multiple transmit pins that are distributed across a mounting surface of the IC chip. Each of the multiple transmit pins is configured to transmit a respective version of the clock signal to one or more off-chip devices. Multiple receiver pins are distributed across the mounting surface of the IC chip and correspond to the multiple transmit pins. Each of the multiple receiver pins is configured to receive respective arrival clock signals from the one or more off-chip devices. Delay compensation circuitry is coupled to the clock interface circuitry and includes multiple delay circuits. Each delay circuit is configured to delay a given clock signal fed to a given transmit pin by a given delay value to establish global timing alignment of the arrival clock signals at the one or more external devices.

In some embodiments of the present disclosure, a delay locked loop includes a coarse delay circuit configured to delay a reference clock signal to generate a first clock signal, a fine delay circuit configured to delay the first clock signal to generate a second clock signal, a first delay circuit configured to delay the second clock signal to generate a third clock signal, a second delay circuit configured to delay the first clock signal to generate a fourth clock signal, a third delay circuit configured to delay the fourth clock signal to generate a fifth clock signal, a phase detector configured to detect a phase difference between the reference clock signal and the fifth clock signal, and a controller configured to adjust, a first delay amount of the coarse delay circuit, a second delay amount of the fine delay circuit and a third delay amount of the third delay circuit.

In some embodiments of the present disclosure, a delay locked loop includes a coarse delay circuit configured to delay a reference clock signal to generate a first clock signal, a fine delay circuit configured to delay the first clock signal to generate a second clock signal, a first delay circuit configured to delay the second clock signal to generate a third clock signal, a second delay circuit configured to delay the first clock signal to generate a fourth clock signal, a third delay circuit configured to delay the fourth clock signal to generate a fifth clock signal, a phase detector configured to detect a phase difference between the reference clock signal and the fifth clock signal, and a controller configured to adjust, a first delay amount of the coarse delay circuit, a second delay amount of the fine delay circuit and a third delay amount of the third delay circuit.

The present disclosure is directed to a digital phase-locked loop frequency synthesizer including: a digitally controlled voltage-controlled oscillator (DCO); a reference oscillator; a digital phase detector; a DCO control module comprising a plurality of registers each arranged to control the frequency of the signal with a predetermined resolution; a first feedback loop arranged to provide a first feedback path between the output of the DCO and the digital phase detector; and a second feedback loop arranged to provide a second feedback path between the first register output and the second register input, the second feedback loop comprising an adder module arranged to change a value of the second register based on the first register output to maximize a DCO frequency output range provided by the first register.