A frequency determination device for determining a frequency relationship between a reference signal and a clock signal. Each constituent TDC is configured to provide a digitally represented constituent output signal in response to receiving a constituent reference signal and a constituent clock signal, and the frequency determination device is configured to successively provide respectively delayed versions of the constituent clock signal of a first constituent TDC as respective constituent clock signals to the other constituent TDC:s. The reference signal provider is configured to provide the respective constituent reference. The switching circuitry is configured to provide the reference signal as the constituent clock signal to the first constituent TDC. The determination circuitry is configured to determine a number of consecutively same-valued symbols in a concatenation of the digitally represented constituent output signals of the constituent TDC:s, and to determine the frequency relationship.

A frequency determination device for determining a frequency relationship between a reference signal and a clock signal. Each constituent TDC is configured to provide a digitally represented constituent output signal in response to receiving a constituent reference signal and a constituent clock signal, and the frequency determination device is configured to successively provide respectively delayed versions of the constituent clock signal of a first constituent TDC as respective constituent clock signals to the other constituent TDC:s. The reference signal provider is configured to provide the respective constituent reference. The switching circuitry is configured to provide the reference signal as the constituent clock signal to the first constituent TDC. The determination circuitry is configured to determine a number of consecutively same-valued symbols in a concatenation of the digitally represented constituent output signals of the constituent TDC:s, and to determine the frequency relationship.

Examples relate to a digitally controlled oscillator circuit arrangement, a digitally controlled oscillation means, a method for a digitally controlled oscillator, a digital loop filter circuit arrangement, a digital loop filtering means, a method for a digital loop filter, a phase locked loop circuit arrangement and phase locked loop, a user device and a base station. The digitally controlled oscillator circuit arrangement comprises input circuitry for obtaining a frequency setting signal, the frequency setting signal comprising a plurality of signal components, selection circuitry for selecting one signal component of the plurality of signal components of the frequency setting signal based on an oscillation signal of the digitally controlled oscillator circuit arrangement, wherein the selection circuitry comprises counting circuitry and multiplexing circuitry, signal generation circuitry for generating the oscillation signal based on the selected signal component of the frequency setting signal, and output circuitry for providing the oscillation signal.

Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

The present disclosure relates to the technical field of integrated circuits, and specifically to a delay-locked loop, a control method for a delay-locked loop, and an electronic device. The delay-locked loop includes: a secondary path configured to perform frequency division on an input clock signal to generate a frequency-divided clock signal, adjust the frequency-divided clock signal having a first frequency to obtain an output clock signal in a locking process of the delay-locked loop, and adjust the frequency-divided clock signal to make the frequency-divided clock signal have a second frequency when the delay-locked loop is locked in a standby state, wherein the second frequency is lower than the first frequency; and a primary path configured to output, when obtaining a target instruction, an output clock replica signal having a same phase as the output clock signal.

The present disclosure relates to the technical field of integrated circuits, and specifically to a delay-locked loop, a control method for a delay-locked loop, and an electronic device. The delay-locked loop includes: a secondary path configured to perform frequency division on an input clock signal to generate a frequency-divided clock signal, adjust the frequency-divided clock signal having a first frequency to obtain an output clock signal in a locking process of the delay-locked loop, and adjust the frequency-divided clock signal to make the frequency-divided clock signal have a second frequency when the delay-locked loop is locked in a standby state, wherein the second frequency is lower than the first frequency; and a primary path configured to output, when obtaining a target instruction, an output clock replica signal having a same phase as the output clock signal.

Phase Locked Loop, PLL, circuitry comprising a phase detector configured to generate a first pulse signal comprising at least one first pulse, a property of each first pulse being indicative of a phase difference between a reference signal and a feedback signal; a pulse repeater circuit configured, based on the first pulse signal, to generate a second pulse signal comprising, for each first pulse, a second pulse generated by repeating the corresponding first pulse; and an oscillator configured to generate the feedback signal and control a frequency of the feedback signal based on the second pulse signal.

Some examples relate to a frequency synthesizer. The frequency synthesizer includes an oscillator including an input terminal and an output terminal. A frequency locked-loop or phase-locked loop (FLL/PLL) unit is arranged on a feedback path extending between the output terminal of the oscillator and the input terminal of the oscillator. A switching unit is configured to selectively switch between a first mode of operation in which the feedback path is closed and the FLL/PLL unit is coupled to the input terminal of the oscillator, and a second mode of operation in which the feedback path is open and a ramping unit is coupled to the input terminal of the oscillator while the feedback path is open.

A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.