A two-point modulation Phase-Locked Loop (PLL) has a dual-input Voltage-Controlled Oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to an offset Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. The loop path through the VCO has a higher gain than the DAC path through the VCO, which has better linearity. A calibration unit divides the VCO output and counts pulses. The offset DAC has a data input and a gain input. During calibration, the data input of the DAC is set to minimum and then maximum values and VCO output pulses counted, and repeated for two values of the gain input to the DAC. From the four counts a K(DAC) calculator calculates the calibrated gain to apply to the gain input of the offset DAC.

In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

A framework for power management. The framework includes at least one power distribution board disposed within a radio-frequency (RF) cabin of a medical imaging system and coupled to an external reference clock. The power distribution board may include a clock circuit that generates one or more output clock signals based on a reference clock signal from the external reference clock. One or more switching regulators may be coupled to the clock circuit. The one or more switching regulators may be synchronized to the one or more output clock signals and provide power to one or more endpoint loads.

A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.

An oscillator includes a tunable oscillator, a phase detector circuit communicatively coupled with an output of the tunable oscillator and an input to the oscillator, and an oscillator controller circuit configured to adjust frequency of the tunable oscillator based upon phase detection between output of the tunable oscillator and output of an external resonant element received at the input to the oscillator.

An oscillator includes a tunable oscillator, a phase detector circuit communicatively coupled with an output of the tunable oscillator and an input to the oscillator, and an oscillator controller circuit configured to adjust frequency of the tunable oscillator based upon phase detection between output of the tunable oscillator and output of an external resonant element received at the input to the oscillator.

Disclosed as a clock alignment module for a near field communication, NFC, controller operable in active load modulation, ALM, card mode, the module being operable during a transmit mode comprising transmit bursts and comprising: an input for receiving a field clock signal (CLK_FIELD); an output for outputting a local controller clock signal (CLK_FB); a transmit envelop unit configured to determine whether a time since an end of a latest transmit burst exceeds a threshold, Tdelay; and a phase locked loop, PLL, configured to selectively lock the phase of the local controller clock signal to the phase of the field clock signal, in response to the time exceeding the threshold and a next transmit burst not having started. Associated NFC controllers, integrated circuits and methods are also disclosed.

A clock recovery circuit includes a multi-phase sampling circuit, a phase comparison circuit, a recovery clock generation circuit, and a phase shifter. The multi-phase sampling circuit includes edge samplers and data samplers. A data signal is input to each of the edge samplers and each of the data samplers. The phase comparison circuit is disposed at an output side of the multi-phase sampling circuit. The recovery clock generation circuit is configured to output multi-phase clock signals. The phase shifter is disposed between the recovery clock generation circuit and the multi-phase sampling circuit and configured to generate a plurality of clock signals to be supplied to the multi-phase sampling circuit by shifting a phase of a first one of the multi-phase clock signals output from the recovery clock generation circuit by a shift amount different from a shift amount of a second one of the multi-phase clock signals.

A clock recovery circuit includes a multi-phase sampling circuit, a phase comparison circuit, a recovery clock generation circuit, and a phase shifter. The multi-phase sampling circuit includes edge samplers and data samplers. A data signal is input to each of the edge samplers and each of the data samplers. The phase comparison circuit is disposed at an output side of the multi-phase sampling circuit. The recovery clock generation circuit is configured to output multi-phase clock signals. The phase shifter is disposed between the recovery clock generation circuit and the multi-phase sampling circuit and configured to generate a plurality of clock signals to be supplied to the multi-phase sampling circuit by shifting a phase of a first one of the multi-phase clock signals output from the recovery clock generation circuit by a shift amount different from a shift amount of a second one of the multi-phase clock signals.

A phase-locked loop (PLL) performs hitless switching from a first reference clock (ref1) to a second reference clock (ref2) by entering holdover mode (418), and aligning the feedback clock (fbclk) to the second reference clock while in holdover mode. The alignment is performed by adjusting a divisor input (D) for the multi-mode divider (128) that divides the output clock frequency (PLLout) to generate the feedback clock. Other features are also provided.