A device, particularly a radar sensor, has a voltage-controlled oscillator for generating a high-frequency signal which has an actual frequency, a voltage adjusting device to control the oscillator, and a calibration device operable for adjusting a voltage value which is assigned to a value of a target frequency. The calibration device is operable for finding a difference between a frequency and the target frequency corresponding to the voltage set at the oscillator. The calibration device is also operable for generating a low-frequency signal from the high-frequency signal, determining the oscillation period of the low-frequency signal, calculating an auxiliary frequency from the oscillation period of the low-frequency signal, wherein the auxiliary frequency corresponds to the actual frequency of the high-frequency signal, and for adjusting the voltage value assigned to the target frequency according to the frequency difference between the auxiliary frequency and the target frequency.

A device, particularly a radar sensor, has a voltage-controlled oscillator for generating a high-frequency signal which has an actual frequency, a voltage adjusting device to control the oscillator, and a calibration device operable for adjusting a voltage value which is assigned to a value of a target frequency. The calibration device is operable for finding a difference between a frequency and the target frequency corresponding to the voltage set at the oscillator. The calibration device is also operable for generating a low-frequency signal from the high-frequency signal, determining the oscillation period of the low-frequency signal, calculating an auxiliary frequency from the oscillation period of the low-frequency signal, wherein the auxiliary frequency corresponds to the actual frequency of the high-frequency signal, and for adjusting the voltage value assigned to the target frequency according to the frequency difference between the auxiliary frequency and the target frequency.

An apparatus comprises a digitally controlled circuit having a variable capacitance and a controller configured to adjust a magnitude of the variable capacitance of the digitally controlled circuit. The digitally controlled circuit comprises a plurality of gain elements, the plurality of gain elements comprising one or more positive voltage-to-frequency gain elements and one or more negative voltage-to-frequency gain elements. The controller is configured to adjust the magnitude of the capacitance by adjusting the gain provided by respective ones of the gain elements in an alternating sequence of the positive voltage-to-frequency gain elements and the negative voltage-to-frequency gain elements.

An apparatus includes circuitry and an oscillator circuit that may be configured to generate a clock signal dependent upon a control signal. The circuitry may be configured to perform a frequency measurement of the clock signal. In response to a determination that the frequency of the clock signal is greater than a first threshold, the circuitry may also be configured to perform a phase comparison between a divided clock signal and a reference clock signal, and to adjust a value of the control signal such that the adjusted value depends upon a result of the comparison. In response to a determination that the frequency of the clock signal is less than the first threshold, the circuitry may be configured to adjust the value of the control signal such that the adjusted value depends upon a result of the measurement.

To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.

A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.

Performance indicator circuitry is provided for characterizing performance of a phase locked loop (PLL) in a phase path of a polar modulator or polar transmitter that is used to generate a phase modulated RF signal. The PLL includes an oscillator, a high pass path, and a low pass path. The low pass path includes a loop filter. The performance indicator circuitry includes first input circuitry and parameter calculation circuitry. The first input circuitry is configured to input a loop filter signal from the loop filter. The parameter calculation circuitry is configured to compute a value for a performance indicator based on the loop filter signal and control or characterize an aspect of operation of the PLL based on the value.

The invention concerns an apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate an enable signal in response to (i) a comparison of a width of an up pulse and a pre-determined width and (ii) a comparison of a width of a down pulse and the pre-determined width. The up pulse and the down pulse may be generated in response to a comparison of a feedback signal and a reference signal. The enable signal may be active when both the comparisons are within a pre-determined threshold. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active.

A device for generating first clock signals includes first circuits, each including a ring oscillator delivering one of the first clock signals and being connected to a first node configured to receive a first current. A circuit selects one the first clock signals, and a phase-locked loop delivers a second signal which is a function of a difference between a frequency of the first selected clock signal and a set point frequency. Each first circuit supplies the first node with a compensation current determined by the second signal, when this first circuit delivers the selected clock signal and operates in controlled mode.

A signal generator includes a processing unit. The signal generator is configured to generate at least one periodic output signal. The output signal comprises a triangular-waveform signal. A frequency and an amplitude of the output signal are adjustable. The signal generator is configured to receive an input parameter. The input parameter comprises at least one piece of information about a setpoint amplitude and a setpoint frequency of the output signal. The processing unit is configured to determine a signal direction of the output signal. The processing unit is configured to determine a step size. The processing unit is configured to apply the step size to an actual amplitude based on the signal direction for a number of clock cycles. The number of clock cycles is dependent on the setpoint frequency of the output signal.