A synchronization circuit may include: a delay line configured to delay a reference clock signal; a division circuit configured to generate a divided feedback clock signal by dividing a feedback clock signal at a division ratio which is set according to a division ratio control signal; a phase detection circuit configured to generate a phase detection signal by detecting the phase of the divided feedback clock signal based on the reference clock signal; and a delay line control circuit configured to control a delay time of the delay line according to the phase detection signal and the divided feedback clock signal.

A synchronization circuit may include: a delay line configured to delay a reference clock signal; a division circuit configured to generate a divided feedback clock signal by dividing a feedback clock signal at a division ratio which is set according to a division ratio control signal; a phase detection circuit configured to generate a phase detection signal by detecting the phase of the divided feedback clock signal based on the reference clock signal; and a delay line control circuit configured to control a delay time of the delay line according to the phase detection signal and the divided feedback clock signal.

This technology is to enable high quality audio reproduction on the reception side without supplying a transmission clock using a clock signal line from the reception side to the transmission side. The transmission apparatus receives encoded data capable of clock recovery from a reception apparatus (external device), generates an audio clock on the basis of a carrier clock recovered from the encoded data, and transmits audio data to the reception apparatus in synchronization with the audio clock. The reception apparatus transmits the encoded data capable of clock recovery to the external device in synchronization with the carrier clock generated on the basis of an self-generating audio clock, receives the audio data from the transmission apparatus (external device), and processes the audio data on the basis of the self-generating audio clock.

This technology is to enable high quality audio reproduction on the reception side without supplying a transmission clock using a clock signal line from the reception side to the transmission side. The transmission apparatus receives encoded data capable of clock recovery from a reception apparatus (external device), generates an audio clock on the basis of a carrier clock recovered from the encoded data, and transmits audio data to the reception apparatus in synchronization with the audio clock. The reception apparatus transmits the encoded data capable of clock recovery to the external device in synchronization with the carrier clock generated on the basis of an self-generating audio clock, receives the audio data from the transmission apparatus (external device), and processes the audio data on the basis of the self-generating audio clock.

The present application proposes a method of locating oscillation sources of wind power integrated system based on energy spectrums. The method include: collecting information of voltage and current at the terminal of each generator and obtaining a dynamic energy curve of each generator over time; choosing the generators whose curve shows an upward trend in the dynamic energy over time curve into alternative generators; obtaining and processing energy spectrums of synchronous generator, DFIG with PLL, and/or an analogical energy spectrum of DFIG with virtual inertia among the alternative generators; selecting generator with maximum proportion of dominant oscillation mode as an oscillation source reference generator; and calculating the similarity coefficients between energy spectrums of each remaining candidate generator and the oscillation source reference generator, determining the oscillation source generators.

The present application proposes a method of locating oscillation sources of wind power integrated system based on energy spectrums. The method include: collecting information of voltage and current at the terminal of each generator and obtaining a dynamic energy curve of each generator over time; choosing the generators whose curve shows an upward trend in the dynamic energy over time curve into alternative generators; obtaining and processing energy spectrums of synchronous generator, DFIG with PLL, and/or an analogical energy spectrum of DFIG with virtual inertia among the alternative generators; selecting generator with maximum proportion of dominant oscillation mode as an oscillation source reference generator; and calculating the similarity coefficients between energy spectrums of each remaining candidate generator and the oscillation source reference generator, determining the oscillation source generators.

The present disclosure describes current steering phase control for current-mode logic (CML) circuits. In some aspects, a circuit for frequency division comprises a current sink connected to a ground rail. The circuit also includes first and second current-carrying branches of frequency-dividing circuitry operably connected to respective load resistors, which are connected to a power rail. A first switch element of the circuit is connected between the current sink and the first current-carrying branch and a second switch element of the circuit is connected between the current sink and the second current-carrying branch. The first and second switch elements may steer current sank by the current sink between the first and second current-carrying branches effective to alter a phase of a signal provided by the frequency division circuit.

A dual-frequency-output crystal controlled oscillator includes a crystal resonator, an oscillator circuit, a first output terminal, a second output terminal, and a selection circuit. The crystal resonator includes an input terminal for measurement and an output terminal for measurement. The oscillator circuit is configured to amplify an output of the crystal resonator; a first output terminal configured to output a first frequency based on an output from the oscillator circuit. The second output terminal is configured to output a second frequency lower than the first frequency based on the output from the oscillator circuit. The selection circuit is configured to turn on/off an output of the first frequency. The input terminal for measurement is disposed such that a distance between the input terminal for measurement and the second output terminal is longer than a distance between the input terminal for measurement and the first output terminal.

A dual-frequency-output crystal controlled oscillator includes a crystal resonator, an oscillator circuit, a first output terminal, a second output terminal, and a selection circuit. The crystal resonator includes an input terminal for measurement and an output terminal for measurement. The oscillator circuit is configured to amplify an output of the crystal resonator; a first output terminal configured to output a first frequency based on an output from the oscillator circuit. The second output terminal is configured to output a second frequency lower than the first frequency based on the output from the oscillator circuit. The selection circuit is configured to turn on/off an output of the first frequency. The input terminal for measurement is disposed such that a distance between the input terminal for measurement and the second output terminal is longer than a distance between the input terminal for measurement and the first output terminal.

Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.