A temperature-to-digital converter includes a temperature sensor circuit, an analog-to-digital converter (ADC), and a digital processing circuit. The temperature sensor circuit is configured to generate first and second complementary-to-absolute-temperature (CTAT) voltages based on a sensed absolute temperature. The ADC is configured to receive the first and second CTAT voltages. Further, during first and second conversion cycles of the ADC, the ADC is configured to receive the first and second CTAT voltages, and generate first and second digital voltages, respectively. The first and second digital voltages are generated based on the first and second CTAT voltages, respectively, and a difference between the first and second CTAT voltages. The digital processing circuit is configured to generate, based on the first and second digital voltages, a temperature output voltage that is independent of a gain of the ADC and a digital representation of the absolute temperature.

An apparatus includes a first digital-to-time converter (DTC) and a second DTC. The first DTC includes a sequence of delay stages. Each of the delay stages adds a delay to an input signal based on a control signal. Each delay stage includes a comparator and a capacitor coupled to an input of the comparator and to ground. The second DTC is coupled in parallel to the first DTC. The second DTC adds a delay to the input signal based on a complement of the control signal.

An analog to digital conversion (ADC) circuit includes a voltage-controlled oscillator (VCO)-based quantizer that receives a voltage input signal to be quantized and provides a digital output. A predictor samples the digital output, evaluates correlation between successive samples, and predicts a predicted input sample from the correlation to minimize voltage-to-frequency transfer of the VCO. A feedback loop L1 with a digital to analog converter (DAC) receives the predicted input sample, converts it and subtracts it from the voltage input signal. A feedback loop L2 adds the predicted sample to the digital output.

A successive approximation register analog-to-digital converter (SAR ADC) is disclosed, which is configured to receive an analog input signal and provide a digital output signal. The SAR ADC comprises a capacitor bank for successively providing a plurality of signal levels based on a sample value of the analog input signal, wherein each signal level of the plurality is an indicator for a corresponding bit in a corresponding sample of the digital output signal. Furthermore, the SAR ADC comprises controlling circuitry configured to cause the capacitor bank to provide the plurality of signal levels representing a dynamically scaled version of the sample value of the analog input signal. In some embodiments, a respective selector of each capacitor of the capacitor bank is controlled to charge the capacitor using either the sample value of the analog input signal or the sample value of an opposed version of the analog input signal. The setting of the respective selectors corresponds to a digital representation of a scaling value (e.g., a sample value of an oscillator signal) for the dynamically scaled version of the sample value of the analog input signal. Corresponding method, receiver, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).

In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.

Disclosed examples include pipeline ADC, balancing circuits and methods to balance a load of a reference circuit to reduce non-linearity and settling effects for a reference voltage signal, in which balancing capacitors are connected to a voltage source in a pipeline stage ADC sample time period to precharge the balancing capacitors using a voltage above the reference voltage, and a selected set of the precharged balancing capacitors is connected to provide charge to the output of the reference circuit during the second time period.

An analog-to-digital conversion circuit (100) is disclosed. It comprises a switched-capacitor SAR-ADC, (110) arranged to receive an analog input signal (x(t)) and a clock signal, to sample the analog input signal (x(t)), and to generate a sequence (W(n)) of digital output words corresponding to samples of the analog input signal (x(t)), wherein the SAR-ADC (110) is arranged to generate a bit of the digital output word per cycle of the clock signal. It further comprises a clock-signal generator (120) arranged to supply the clock signal to the SAR-ADC (110), and a post-processing unit (140) adapted to receive the sequence (W(n)) of digital output words and generate a sequence of digital output numbers (y(n)), corresponding to the digital output words, based on bit weights assigned to the bits of the digital output words. The bit weights are selected to compensate for a decay of a signal internally in the SAR-ADC (110).

A time-interleaved analogue-to-digital converter including a first analogue-to-digital converter, a second analogue-to-digital converter, and a third analogue-to-digital converter, each arranged to sample an analogue input and produce a respective digital output based on the sampled analogue input, and also including a signal interleaving portion, arranged to combine the digital outputs from the analogue-to-digital converters to produce a digital output signal. The time-interleaved analogue-to-digital converter is configured for operation both in an operational mode, and in a compensation mode when the third analogue-to-digital converter is non-functional. In the operational mode, the first and second analogue-to-digital converter sample the analogue input respectively at a first frequency and a second frequency. In the compensation mode, the first and second analogue-to-digital converter sample the analogue input respectively at a third frequency and a fourth frequency. The third frequency is higher than the first frequency, and the fourth frequency is higher than the second frequency.

An oscillator-based sensor interface circuit includes first and second input nodes arranged to receive first and second electrical signals representative of an electrical quantity, respectively; an analog filter; a first oscillator arranged to receive a first oscillator input signal and a second oscillator different from the first oscillator and arranged to receive a second oscillator input signal; a comparator arranged to compare signals coming from the first and second oscillators; a first feedback element arranged to receive a representation of the digital comparator output signal and to convert the representation into a first feedback signal to be applied to the oscillation means; a digital filter arranged to yield an output signal, being an filtered version of the digital comparator output signal; a second feedback element arranged to receive the output signal and to convert the output signal into a second feedback signal.

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.