An analog-to-digital conversion circuit (100) is disclosed. It comprises a switched-capacitor SAR-ADC, (110) arranged to receive an analog input signal (x(t)) and a clock signal, to sample the analog input signal (x(t)), and to generate a sequence (W(n)) of digital output words corresponding to samples of the analog input signal (x(t)), wherein the SAR-ADC (110) is arranged to generate a bit of the digital output word per cycle of the clock signal. It further comprises a clock-signal generator (120) arranged to supply the clock signal to the SAR-ADC (110), and a post-processing unit (140) adapted to receive the sequence (W(n)) of digital output words and generate a sequence of digital output numbers (y(n)), corresponding to the digital output words, based on bit weights assigned to the bits of the digital output words. The bit weights are selected to compensate for a decay of a signal internally in the SAR-ADC (110).

A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.

A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC, and includes a notch filter. The interference detection path is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter. The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter to attenuate the interference signal.

Disclosed herein are some examples of algorithmic analog-to-digital converters (AADCs) that perform noise shaping. In particular, an AADC disclosed herein includes circuitry that can store residue(s) of one or more conversion cycles produced by the AADC and apply a value corresponding to the residue(s) to a subsequent conversion cycle. The AADC may perform a filtering procedure with the residue(s) to produce the value applied to the subsequent conversion. Applying the value to the subsequent conversion cycle can increase a signal-to-noise ratio of the signal that the AADC is converting in the subsequent conversion cycle.

A time-to-digital converter and a converting method are provided. The time-to-digital converter includes: a phase locked loop unit configured to multiply an input reference clock by using a phase locked loop (PLL); a counting unit configured to count the multiplied input reference clock and record an edge position of an input signal; a delay locked loop unit configured to decompose the multiplied input reference clock into a multi-phase clock using a delay locked loop (DLL), and sense the recorded edge position of the input signal among the decomposed multi-phase clock and record a fine edge position; and a control unit configured to calculate a time difference in time of flight (ToF) between a start signal and a stop signal of the input signal by using the recorded edge position and the recorded fine edge position.

In accordance with the present invention a system and method for calibration of the current steering DAC is elaborated which helps to reduce design complexity and reduce silicon area required in the design. Present invention is utilising a clocked comparator and plurality of switch transistors 405,305 and AUX DAC in conjunction with digital estimator and digital compensator blocks to estimate the errors in the current sources 406 and compensate the errors using same AUX DAC during normal operation mode.

A method for calibrating a successive-approximation analog-to-digital converter (ADC) includes configuring the successive-approximation ADC in a calibration mode of operation. The method includes, while in the calibration mode of operation: determining a digital code corresponding to a programmable capacitance of the successive-approximation analog-to-digital converter, and storing the digital code corresponding to the programmable capacitance in a storage element of an integrated circuit die including the successive-approximation ADC. The programmable capacitance may be a gain tuning capacitance, a bridge tuning capacitance, an offset capacitance, or a monotonicity tuning capacitance.

A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.

Provided is an AD converter including a capacitive DAC, a comparator, and a control logic unit. The capacitive DAC includes first bit capacitors connected in parallel to a first line, second bit capacitors connected in parallel to at least one second line, a connection capacitor connecting the first line and the second line, an adjustment capacitor connected to the second line, and a bit correction unit corresponding to at least either the first bit capacitors or the second bit capacitors. The bit correction unit includes a correction capacitor including a first terminal connected to at least one of the first line and the second line. A voltage can be applied to a second terminal of the correction capacitor in conjunction with a first bit capacitor or second bit capacitor corresponding to the correction capacitor among the first bit capacitors and the second bit capacitors.

A tri-level digital-to-analog converter (DAC) element includes a first DAC cell. The first DAC cell includes a first reference circuit, a second reference circuit, and a switch circuit. The first reference circuit provides a first reference signal. The second reference circuit provides a second reference signal. The first switch circuit receives a control input from an input port of the tri-level DAC element, and controls interconnection between the first reference circuit, the second reference circuit, and an output port of the tri-level DAC element according to the control input. During a period in which the tri-level DAC element operates in a 0 state, the first switch circuit is arranged to couple at least one of the first reference circuit and the second reference circuit to the output port of the tri-level DAC element.