A method and a circuit for measuring an absolute voltage signal, such that the circuit comprises: an A/D convertor, and a controller adapted for: a) obtaining a first digital reference value for a first reference signal having a positive temperature coefficient; b) obtaining a second digital reference value for a second reference signal having a negative temperature coefficient; c) obtaining a raw digital signal value for the signal to be measured, while applying a same reference voltage for step a) to c); and d) calculating the absolute voltage value in the digital domain using a mathematical function of the first and second digital reference value, and the raw digital signal value.

As paths for a current flowing through a conductor, a first current path through which a current flows from a first conductive portion to a second conductive portion, and a second current path through which a current flows from a third conductive portion to the second conductive portion are provided. Each of the first conductive portion, the second conductive portion, and the third conductive portion has a plate shape, a point P1 is located on a plate surface of the first conductive portion, and a point P2 is located on a plate surface of the second conductive portion. A current detecting circuit detects a value related to a potential difference between the points P1 and P2, and outputs a voltage value corresponding to a values of a current flowing through each of the first current path and the second current path.

An example analog-to-digital converter (ADC) comprising: sample and hold circuitry coupled to an analog input; a first sub-ADC coupled to the sample and hold circuitry; a multiplying digital-to-analog converter (M-DAC) coupled to the first sub-ADC; summation circuitry coupled to the sample and hold circuitry and the M-DAC; an amplifier coupled to the summation circuitry; a second sub-ADC coupled to the amplifier; and reference generation circuitry coupled to the first sub-ADC, the M-DAC, and the second sub-ADC, the reference generation circuitry including: reference voltage circuitry coupled to the M-DAC; a first resistor coupled to the reference voltage circuitry; a second resistor coupled to the first resistor; and a capacitor coupled in parallel to the second resistor by a switch.

Disclosed herein are multi-mode methods and devices for sample generation. An exemplary device for generating an output sample includes an analog-to-digital converter (ADC) for sampling a plurality of input analog signals and producing an ADC output sample. The ADC may include a ADC digital modulator including timing-critical components. A plurality of digital blocks may be coupled to the ADC digital modulator. The exemplary device may include a baseband processor for controlling a plurality of clock inputs. The plurality of clock inputs may drive the ADC digital modulator and the plurality of digital blocks. The baseband processor may be configured to operate in a plurality of modes including a first mode and a second mode. The first mode may include a first mode standby state and a first mode initial operating state. The second mode may include a second mode initial operating state and a second mode standby state.

The invention relates to a circuit arrangement comprising a control device, an input circuit for applying an input signal, a conditioning circuit electrically connected to the input circuit for converting the input signal into a measured signal, an analog-to-digital converter electrically connected to the conditioning circuit for converting the measured signal into a digital value, and a reference source that outputs a known reference signal. In this respect, a first switching apparatus is provided that selectively separate the input signal from the conditioning circuit or supplies it to the conditioning circuit and a second switching apparatus is provided that selectively supplies the reference signal to the input circuit or separates it from the input circuit, wherein the control device is configured to determine an offset error and to determine a gain error of the circuit arrangement.

Embodiments are provided for a method of operating a receiver system, the receiver system comprising one or more channels, the method comprising: monitoring a residual DC (direct current) offset in a present channel by sampling an output of an analog-to-digital converter (ADC) of the present channel; adjusting a DCO (direct current offset) correction signal that corresponds to the residual DC offset in response to an absolute value of the residual DC offset exceeding a programmable DCO threshold; and subtracting the DCO correction signal from an analog signal provided to the ADC to reduce the residual DC offset below the programmable DCO threshold.

An input buffer circuit for an analog-to-digital converter is provided. The input buffer circuit includes a buffer amplifier. The buffer amplifier includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair for the analog-to-digital converter. The buffer amplifier further includes a first output node and a second output node each configured to output a respective one of a first buffered signal and a second buffered signal. In addition, the input buffer circuit includes feedback circuitry. The feedback circuitry is configured to generate, based on the first buffered signal and the second buffered signal, a first feedback signal and a second feedback signal for mitigating a respective unwanted signal component at the first input node and the second input node related to a limited reverse isolation of the amplifier buffer. The feedback circuitry is further configured to supply the first feedback signal to the first input node and the second feedback signal to the second input node.

An analog-to-digital converter (ADC) system is provided. The ADC system includes a first signal path. The first signal path includes a first ADC configured to generate first digital data based on an input signal. The first ADC is a time-interleaved ADC including a plurality of sub-ADCs. The first signal path further includes circuitry configured to output activity data indicating at least which of the plurality of sub-ADCs is currently active. The ADC system further includes a correction circuit configured to output digital correction data based on the activity data. Further, the ADC system includes a second signal path coupled in parallel to the first signal path. The second signal path includes a second ADC configured to generate second digital data based on the input signal and a combiner circuit configured to generate modified second digital data by combining the second digital data and the correction data. The ADC system further includes an equalizer configured to generate an equalized output signal of the ADC system based on the first digital data. The equalizer is configured to adjust, based on the modified second digital data, at least one equalization parameter used for generating the equalized output signal of the ADC system.

The present invention provides a device and method for correcting error estimation of an analog-to-digital converter. The method comprises: according to a preset initial value of a correction parameter, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to the initial value of a correction parameter, correcting a gain error between channels, generating a general correction signal, buffering the general correction signal and triggering a counting cell to start counting, and meanwhile calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting up to a preset value, setting enable ends of a low-pass filter accumulating cell and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching the error estimation result, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching the updated clock correction parameter and gain correction parameter, and resetting to carry out cyclic estimation correction. According to the present invention, in the case where a few effective sample points are used, the estimation accuracy is improved and the convergence rate of the estimation correction is increased.

Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each input line to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2.sup.x where x ranges from 0 to m1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than V.sub.ADC.sub._.sub.fs/128+V.sub.ADC.sub._.sub.fs/256+V.sub.ADC.sub._.sub.fs/512+V.sub.ADC.sub._.sub.fs/1024 when m equals 4 and where V.sub.ADC.sub._.sub.fs is the full-scale voltage of the ADC.