An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a skew adjusting circuit. The ADC circuits convert an input signal according to clock signals, to generate first quantized outputs. The calibration circuit calibrates the first quantized outputs to generate second quantized outputs. The skew adjusting circuit includes an estimating circuit and a feedback circuit. The estimating circuit analyzes the second quantized outputs to generate detection signals, wherein the detection signals are related to time difference information of the clock signals. The skew adjusting circuit outputs the detection signals as adjustment signals, wherein the adjustment signals are configured to reduce a clock skew of the ADC circuits. The feedback circuit analyzes the detection signals generated by the estimating circuit, to generate a feedback signal to the estimating circuit, wherein the estimating circuit is configured to adjust the detection signals according to the feedback signal.

An analog-to-digital converter (ADC) system includes a main ADC, a reference ADC, a sampling control circuit, and a calibration circuit. The main ADC obtains a first sampled input voltage by sampling an analog input according to a first sampling clock, and performs analog-to-digital conversion upon the first sampled voltage to generate a first sample value. The reference ADC obtains a second sampled voltage by sampling the analog input according to a second sampling clock, and performs analog-to-digital conversion upon the second sampled voltage to generate a second sample value. The sampling control circuit controls the second sampling clock to ensure that the second sampling clock and the first sampling clock have a same frequency but different phases, and adjusts the second sample value to generate a reference sample value. The calibration circuit applies calibration to the main ADC according to the first sample value and the reference sample value.

An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. Each channel receives a sampling clock with a different phase delay. The sampling clocks are overlapping multi-phase clocks rather than non-overlapping. Overlapping the multi-phase clocks allows the sampling pulse width to be enlarged, providing more time for the sampling switch to remain open and allow analog voltages to equalize through the sampling switch. Higher sampling-clock frequencies are possible than when non-overlapping clocks are used. The sampling clock is boosted in voltage by a bootstrap driver to increase the gate voltage on the sampling switch, reducing the ON resistance. Sampling clock and component timing skews are reduced to one LSB among all N channels.

An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. In each channel the ADC output is filtered, and a product derivative correlator generates a product derivative factor for correlation to two adjacent ADC channels. A matrix processor arranges the product derivative factors from the product derivative correlators into a matrix that is multiplied by a correlation matrix. The correlation matrix is a constant generated from an N×N shift matrix. The matrix processor outputs a sign-bit vector. Each bit in the sign-bit vector determines when tested SAR bits are set or cleared to adjust a channel's variable delay. Sampling clock and component timing skews are reduced to one LSB among all N channels.

A sampling clock generating circuit and an analog to digital converter includes a resistance variable circuit, a NOT-gate type circuit, and a capacitor, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T; an output end of the NOT-gate type circuit is connected to one end of the capacitor; the other end of the capacitor is grounded; a power supply terminal of the NOT-gate type circuit is connected to a power supply; a ground terminal of the NOT-gate type circuit is connected to one end of the resistance variable circuit; and the other end of the resistance variable circuit is grounded; the NOT-gate type circuit is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level.

A device includes at least two digital-to-analog converters, each digital-to-analog converter having a digital-to-analog converter clock modulator, a system reference clock modulator, and a phase detector to track the phases of the clock and the system reference clock. A method of calibrating a phase detector includes providing a pulse waveform, aligning a phase of a digital-to-analog clock to a phase of an internal system reference clock, aligning a phase of a modulated system reference clock with a phase of a modulated, divided, digital-to-analog clock, storing the aligned phase of the modulated system reference clock as a calibration value, synchronizing the digital-to-analog converters and adjusting the phase of the digital-to-analog converters to a center of a desired phase, and storing the aligned phase of the digital-to-analog converters as a calibration value.

A signal processing apparatus includes a plurality of time-interleaving digital-to-analog converters each configured to sample a digital input signal at a preset sub-DAC sample frequency, and to generate an analog sub-DAC output signal. The signal processing apparatus includes analog multiplexer that samples the plurality of sub-DAC output signals at a preset multiplexer clock frequency and generates a multiplexer output signal. The signal processing apparatus further includes a local ADC that receives the multiplexer output signal and generate a digital feedback signal. The signal processing apparatus further includes a digital compensation engine that receives the digital feedback signal from the local ADC and determine one or more distortion compensation parameters. The signal processing apparatus further includes a digital pre-processing stage that receives the one or more distortion compensation parameters from the digital compensation engine and performs distortion compensation pre-processing on the digital input signal.

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a skew adjusting circuit. The ADC circuits convert an input signal according to clock signals, to generate first quantized outputs. The calibration circuit calibrates the first quantized outputs to generate second quantized outputs. The skew adjusting circuit includes an estimating circuit and a feedback circuit. The estimating circuit analyzes the second quantized outputs to generate detection signals, wherein the detection signals are related to time difference information of the clock signals. The skew adjusting circuit outputs the detection signals as adjustment signals, wherein the adjustment signals are configured to reduce a clock skew of the ADC circuits. The feedback circuit analyzes the detection signals generated by the estimating circuit, to generate a feedback signal to the estimating circuit, wherein the estimating circuit is configured to adjust the detection signals according to the feedback signal.

A multi-layer time-interleaving (TI) device and method of operation therefor. This device includes a plurality of TI layers configured to receive a plurality of input clock signals and to output a plurality of output clock signals, each of which can be configured to drive subsequent devices. The layers include at least a first and second layer including a fine-grain propagation device and a barrel-shifting propagation device configured to retime the plurality of input clock signals to produce divided output clock signals. The device can include additional barrel-shifting propagation devices to time interleave an initial two layers to produce one or more additional layers. Using negative phase stepping, the plurality of output clock signals is produced with optimal timing margin and synchronized on a single clock edge.

A sort-and-delay time-to-digital converter (TDC) is provided, made up of a plurality of serially connected sort-and-delay circuits. Each sort-and-delay circuit accepts a time-differential input signal with a first edge separated from a second edge by an input duration of time. The first and second edges are selectively routed as a time-differential output signal with a delayed edge separated from a trailing edge by an output duration of time representing a compression of the input duration of time. Each sort-and-delay circuit also supplies a TDC coded bit (e.g., Gray code) indicating the order in which the first and second edges are routed as leading and trailing edges. The TDC outputs a digital output signal representing the initial input duration of time associated with the initial time-differential input signal received by the initial sort-and-delay circuit. Associated TDC, sort-and-delay, and time amplification methods are also provided.