A time interleaved analog-to-digital converter (TIADC) is provided. The TIADC converts an input signal into a digital output signal and includes N analog-to-digital converters (ADCs), a clock generation circuit, and a control circuit. The N ADCs receive the input signal and sample the input signal according to N sampling clocks to each generate a digital output code, N being an integer greater than or equal to 2. The clock generation circuit is configured to receive a working clock and a set of control values and to generate the N sampling clocks according to the set of control values and the working clock. The control circuit is configured to periodically generate the set of control values based on a pseudo random number and to output the digital output codes in turn as the digital output signal.

Described are apparatus and methods for analog to digital converter (ADC) with factoring and background clock calibration. An apparatus includes an ADC configured to sample and convert differential input signals using a reference clock to obtain a defined number of samples during a first state in an acquisition clock cycle, and a finite state machine circuit configured to obtain the defined number of samples from the ADC using a clock based on the reference clock, factor the defined number of samples based on at least a common mode offset associated with the ADC, and send offset factored output to a controller.

The present invention discloses a method of calibrating time interleaved analog to digital converter comprising: sampling a common input signal, said sampling is performed by an array of sub analog to digital converters, each generating individual digital analog equivalent outputs with sampling time errors, said digital outputs are fed to sampling time error estimation circuitry to calculate a digital output proportional to sampling time error between two consecutive channels, without any restriction on input signal or ADC channel design, said timing skew estimator circuitry composed of generating a delayed output of one of the two consecutive ADC channels, channel first and channel second and subtracting the said delayed output with digital output of the said second channel and producing the first subtracted output and output of said second channel subtracted with said first channel output delayed by sampling delay between the two consecutive channels and producing the second subtracted delayed output, absolute value of the said first subtracted output and said second subtracted delayed output is monitored for peak value of both for a fixed time duration and then subtracted values of the said peak values are the estimation of sampling time error between the said two consecutive channels, same process is repeated to each consecutive ADC channels of the said ADC array.

An analog-to-digital converter (1) includes an S/H circuit (10) that samples and holds an analog input signal in synchronization with a first sampling clock signal (CLK1), a filter circuit (20) that smooths an output signal of the S/H circuit (10), and an ADC circuit (30) that samples an output signal of the filter circuit (20) in synchronization with a second sampling clock signal (CLK2) different from the first sampling clock signal (CLK1), and outputs a digital signal corresponding to an amplitude of the output signal that is sampled.

A multi-instance time-interleaving (TI) system and method of operation therefor. The system includes a plurality of TI devices, each with a plurality of clock generation units (CGUs) coupled to an interleaver network. Within each TI device, the plurality of CGUs provides a plurality of clock signals needed by the interleaver network. A phase detector device is coupled to the plurality of TI devices and configured to determine any phase differences between the clock signals of a designated reference TI device and the corresponding clock signals of each other TI device. To determine the phase differences, the phase detector can use a logic comparator configuration, a time-to-digital converter (TDC) configuration, or an auto-correlation configuration. The phases of the clock signals of each other TI device can be aligned to the reference TI device using internal phase control, retimers, delay cells, finite state machines, or the like.

An analog-to-digital conversion circuit includes; a first analog-to-digital converter (ADC), a second ADC and a third ADC collectively configured to perform conversion operations according to a time-interleaving technique, and a timing calibration circuit configured to calculate correlation values and determine differences between the correlation values using first samples generated by the first ADC, second samples generated by the second ADC, and third samples generated by the third ADC during sampling periods, wherein the timing calibration circuit is further configured to control a phase of a clock signal applied to the second ADC in response to a change in absolute value related to the differences generated during the sampling periods.

For cross-channel spectral analysis of measurement data from multiple recording units with independent sampling clocks, a processing method corrects phase mismatch between the data received over the different channels. Blocks of sampled measurement data are buffered in a hardware logic circuit and timestamps are associated with successive blocks through a hardware interrupt to a GPS receiver of each recording unit. For each first channel data block, the block's starting point, a closest point in time in a data block of the second channel, and the starting point of that second channel data block are determined, using GPS timestamps associated with those data blocks, nominal sampling rate and block size. Phase correction based on the time offset between starting points of the pairs of data blocks and the interval between starting points of successive blocks is applied in the frequency domain after a time-to-frequency domain transformation. Multiple frames of phase-corrected spectra may then be averaged. Only a subset of samples in each data block need be used based upon a specified overlap ratio.

A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The front-end circuit may generate an equalized signal using multiple signals that encode a serial data stream of multiple data symbols. Based on a baud rate of the serial data stream, a determined number of the multiple analog-to-digital converter circuits sample, using a recovered clock signal, the equalized signal at the respective times to generate corresponding samples. The recovery circuit generates, using the samples, the recovered clock signal and recovered data symbols.

An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. In each channel the ADC output is filtered, and a product derivative correlator generates a product derivative factor for correlation to two adjacent ADC channels. A matrix processor arranges the product derivative factors from the product derivative correlators into a matrix that is multiplied by a correlation matrix. The correlation matrix is a constant generated from an N×N shift matrix. The matrix processor outputs a sign-bit vector. Each bit in the sign-bit vector determines when tested SAR bits are set or cleared to adjust a channel's variable delay. Sampling clock and component timing skews are reduced to one LSB among all N channels.

An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. Each channel receives a sampling clock with a different phase delay. The sampling clocks are overlapping multi-phase clocks rather than non-overlapping. Overlapping the multi-phase clocks allows the sampling pulse width to be enlarged, providing more time for the sampling switch to remain open and allow analog voltages to equalize through the sampling switch. Higher sampling-clock frequencies are possible than when non-overlapping clocks are used. The sampling clock is boosted in voltage by a bootstrap driver to increase the gate voltage on the sampling switch, reducing the ON resistance. Sampling clock and component timing skews are reduced to one LSB among all N channels.