A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC, and includes a notch filter. The interference detection path is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter. The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter to attenuate the interference signal.

An ultra-wideband distributed ADC can be cascaded to build high performance radio frequency (RF) analog electronics integrated with advanced digital complementary metal-oxide-semiconductor (CMOS) electronics on the same wafer. Advantages can include wide spectral coverage, high resolution, large dynamic range, and high information processing bandwidth. Part of an overall system includes a precise, programmable, real-time delay circuit that can achieve picosecond accuracy.

Techniques for testing circuits, such as converter circuits, such as digital-to-analog converter circuits (DACs), are described. A digital signal processor (DSP) can generate a waveform, such as sine wave, and apply the sine wave to the circuit under test, e.g., a DAC. The DAC can generate an output and the DSP can regenerate the waveform and determine an accuracy of the DAC such as to determine whether the DAC meets one or more specified criteria. In some example implementations, the tests can be performed using variable voltage amplitude segments.

The present invention discloses a method of calibrating time interleaved analog to digital converter comprising: sampling a common input signal, said sampling is performed by an array of sub analog to digital converters, each generating individual digital analog equivalent outputs with sampling time errors, said digital outputs are fed to sampling time error estimation circuitry to calculate a digital output proportional to sampling time error between two consecutive channels, without any restriction on input signal or ADC channel design, said timing skew estimator circuitry composed of generating a delayed output of one of the two consecutive ADC channels, channel first and channel second and subtracting the said delayed output with digital output of the said second channel and producing the first subtracted output and output of said second channel subtracted with said first channel output delayed by sampling delay between the two consecutive channels and producing the second subtracted delayed output, absolute value of the said first subtracted output and said second subtracted delayed output is monitored for peak value of both for a fixed time duration and then subtracted values of the said peak values are the estimation of sampling time error between the said two consecutive channels, same process is repeated to each consecutive ADC channels of the said ADC array.

The present disclosure provides an error compensation correction system and method for an analog-to-digital converter with a time interleaving structure, the system includes an analog-to-digital converter with a time interleaving structure, a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall MUX circuit. Through the error compensation correction system and method for the analog-to-digital converter with a time interleaving structure according to the present disclosure, lower correction hardware implementation complexity and higher stability are ensured. The system and method according to the present disclosure are particularly suitable for interchannel mismatch error correction of dense channel time interleaving ADC, and the performance of the time interleaving ADC is improved.

Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches. The mismatches can degrade the quality of the analog output. To extract the mismatches, a transparent dither can be used. The mismatches can be extracted by observing the analog output, and performing a cross-correlation of the observed output with the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the mismatches.

A transceiver system includes a clock generator and an analog-to-digital circuit (ADC). The transceiver system also includes a coupling correction circuit coupled to the clock generator and to the ADC, wherein the coupling correction circuit is configured to provide an in-phase correction and a quadrature-phase correction to a signal received by the ADC.

Analog gain correction circuitry and analog switching clock edge timing correction circuitry can provide coarse correction of interleaving errors in radio-frequency digital-to-analog converters (RF DACs), such as may be used in 5G wireless base stations. The analog correction can be supplemented by digital circuitry configured to pre-cancel an interleaving image by adding to a digital DAC input signal a signal equal and opposite to an interleaving image created by the interleaving DAC, such that the interleaving image is effectively mitigated. Error correction control parameters can be periodically adjusted for changes in temperature by a controller coupled to an on-chip temperature sensor. A model useful for understanding the sources of error in interleaving DACs is also described.

Repetitive waveforms are processed to produce an averaged replica of the waveforms by first determining a stream of digital samples, with random time shifts of waveform starts relative to the samples. A mutual arrangement of a trigger signal and a following sample over a succession of sampling periods, enables k sections coinciding with segments [k.Math.T/K, (k+1).Math.T/K]. K is determined and a distance D between the trigger signal and the following sample is calculated. Second, values of the samples are transformed so that waveforms represented by the samples, are shifted in time by D in relation to the sample positions. The mutual positions of the delayed waveforms and the sampling clock along multiple axes, exactly repeats so that values of the produced samples along the axes coincide. The discreet time delays before averaging avoid frequency component distortions in resulting replicas of the waveforms.

A circuit arrangement and methods for reducing a switching noise jitter signature in an output signal of a feedback control loop circuitry are disclosed. The passive signal conditioning means including the rails is closely coupled to the common connection junction and is characterized by a set of specified characteristics to condition pre-existing noise amplitude and slopes of the output signal so as to improve the interactions between the output signal and the feedback control loop circuitry. As a consequence, the switching noise jitter signature, which is produced by transient noise displacement or noise perturbation in the time domain when the output signal jitters, can be reduced in the output of the feedback control loop circuitry.