A rollable display device includes a rollable display and a first protection film disposed on a first surface of the rollable display. The first protection film extends beyond a first display edge of the rollable display. The rollable display device further includes a second protection film disposed on a second surface of the rollable display facing the first surface of the rollable display. The second protection film extends beyond the first display edge of the rollable display. The rollable display device additionally includes a first adhesive layer disposed between the rollable display and the first protection film. The rollable display device further includes second adhesive layer disposed between the rollable display and the second protection film, and a first adhesion part disposed adjacent to the first display edge of the rollable display and between the first protection film and the second protection film.

A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.

In an embodiment a digital-to-analog converter includes a plurality of first capacitors, each having a first electrode and a second electrode, wherein the second electrodes are connected together and are connected to an inverting input of a first amplifier stage having its non-inverting input coupled to ground, a plurality of first switches, each of the first capacitors having its first electrode connected to a corresponding one of the first switches, wherein each of the first switches is configured to occupy a first state where the first electrode of a corresponding first capacitor is coupled to a first reference voltage and occupy a second state where the first electrode of the corresponding first capacitor is coupled to a second reference voltage different from the first reference voltage, a capacitive feedback circuit connected between the inverting input and an output of the first amplifier stage, the capacitive feedback circuit including at least one second capacitor and a controller.

Solid-state image capturing elements are disclosed. In one example, a solid-state image capturing element includes a noise-cancelling-signal generating circuit connected to a pixel power source. It executes a gain change and a polarity inversion on a first noise cancelling signal to output a second noise cancelling signal. The element also includes a DA converter that outputs a reference signal and converts a current of the second noise cancelling signal into a voltage to superpose the converted voltage on the reference signal; a comparator that receives inputs of the reference signal and a pixel signal and outputs an inversion signal according to the pixel signal and a gain setting; a counter that converts an inversion timing of the comparator into a digital value; and a gain controlling unit that outputs, when changing a gradient of the reference signal and an input capacity to execute a gain control on the comparator.

A device is provided comprising a first oscillator based analog-to-digital converter configured to receive an analog input signal and output a first digital signal and a second oscillator based analog-to-digital converter configured to receive an analog reference signal and output a second digital signal. The device further comprises output logic configured to generate a digital output signal based on the first digital signal and the second digital signal.

A disclosed comparator includes a comparison circuit that performs comparison between an input signal and a reference signal and changes a level of a signal to be output to a first node in accordance with a result of the comparison; and a positive feedback circuit including an amplifier unit that includes a current source load and outputs a signal in accordance with a potential of the first node to a second node and a feedback unit that positively feeds back a signal in accordance with a potential of the second node to the first node. The feedback unit includes a first transistor to which output of the amplifier unit is fed back and a switch that controls turning on or off of the first transistor.

A disclosed comparator includes a comparison circuit including a differential unit that compares an input signal with a reference signal and changes a level of a signal output to a first node in accordance with a result of comparison and an amplifier unit that includes a load element and outputs a signal in accordance with a potential of the first node to a second node, and a positive feedback circuit that is connected to the second node and a third node and changes a level of a signal at the third node at a rate higher than a change rate of a level of a signal at the second node in accordance with a change in a level of a signal at the second node.

Saturation of an A/D converter at a receiver is addressed by forcing a controlled clipping of a peak signal pulse in the analog domain and restoring the pulse using a digital algorithm within the receiver. An A/D converter saturates and clips the peak pulses in the signal. Saturated peaks are restored by an algorithm operating in a baseband digital signal processor that utilizes information related to the time intervals where clipping was applied, along with information associated with the portion of the pulse below the clipping threshold. The time interval information is available from the A/D converter or through use of a separate pulse clipping detection algorithm. Through the use of embodiments of the present invention, the effect of signal clipping on receiver performance is reduced and therefore allows for increased clipping of the received signal.

In at least some embodiments, a system comprises a frequency generator configured to generate a second clock signal having a second frequency using a first clock signal having a first frequency. The second frequency is offset from the first frequency and each of a plurality of harmonic frequencies of the second frequency is offset from a harmonic frequency of the first frequency. The system also includes a power converter configured to produce a power signal that at least partially corresponds to the second frequency. The system further comprises an analog-to-digital converter (ADC) configured to sample and convert analog voltages at the first frequency. The ADC is powered by the power signal.

A digital-to-analog converter includes a first current source module configured to supply a current I.sub.1 to the digital-to-analog converter, a first switch control module configured to control connection or disconnection between each branch and a trans-impedance amplifier in the digital-to-analog converter based on a to-be-converted digital signal, where the current I.sub.1 supplied by the first current source module flows to the trans-impedance amplifier through a connected branch, and the trans-impedance amplifier is configured to convert the current I.sub.1 supplied by the first current source module into an analog voltage and output the analog voltage.