An image sensor chip includes an internal voltage generator for generating internal voltages using an external voltage received at a first terminal of the image sensor chip, a temperature sensor for generating a temperature voltage, a selection circuit for outputting one of the external voltage, the internal voltages, and the temperature voltage, a digital code generation circuit for generating a digital code using an output voltage of the selection circuit, and a second terminal for outputting the digital code from the image sensor chip.

The present disclosure provides alternative solutions to the problem of providing a stable voltage reference to high speed ADCs that possess high sampling rates. In one example the high speed amplifier is replaced by a smaller, slower, lower power amplifier in combination with a relatively large capacitor connected to the same node as the amplifier output and the ADC reference input. The capacitor is charged substantially to the external reference voltage and hence keeps the reference input of the ADC almost at the external reference voltage between conversions, such that when conversion is about to occur and the external reference is switched in then very little charge is required from the external reference, and hence the reference signal quickly settles. An alternative arrangement is to replace the amplifier with a comparator that takes as one of its inputs the external reference signal, and as the other of its inputs the internal reference to the ADC, and makes use of a control circuit that adjusts the threshold of the comparator from bit-trial to bit-trial until the internal reference is brought up to substantially the same signal level as the external reference. When the external reference is then switched in to supply the ADC circuit it settles very quickly and draws very little power therefrom.

An analog-to-digital converter includes a low voltage power supply rail, a high voltage power supply rail, successive approximation circuit, a level shifter, and a capacitive digital-to-analog converter (CDAC). The successive approximation circuitry is coupled to the low voltage power supply rail. The level shifter is coupled to the high voltage power supply rail and includes inputs coupled to first outputs of the successive approximation circuitry. The CDAC includes a first segment and a second segment. The first segment includes a first plurality of capacitors, and a first plurality of switches coupled to outputs of the level shifter. The second segment includes a second plurality of capacitors, and a second plurality of switches coupled to second outputs of the successive approximation circuitry.

A digital-to-analog converter includes a resistor ladder, a first switch and a protection circuit. The first switch includes a first terminal and a second terminal that are respectively coupled to a rung of the resistor ladder and a reference voltage node. The protection circuit is coupled to the reference voltage node and to a reference voltage input terminal. The protection circuit includes a second switch, a third switch, and a fourth switch. First and second terminals of the second switch are respectively coupled to the reference voltage node and the reference voltage input terminal. First and second terminals of the third switch are respectively coupled to the reference voltage node and a reference voltage feedback terminal. The first and second terminals of the fourth switch are respectively coupled to the reference voltage input terminal and the reference voltage feedback terminal.

A reference ripple suppression circuit adaptable to a successive approximation register (SAR) analog-to-digital converter (ADC) includes a plurality of code-dependent compensation cells, each including a logic circuit and a compensation capacitor. A first plate of the compensation capacitor is coupled to receive a reference voltage to be compensated, and a second plate of the compensation capacitor is coupled to receive an output of the logic circuit performing on an output code of the SAR ADC and at least one logic value representing a bottom-plate voltage of a switched digital-to-analog converter (DAC) of the SAR ADC. (k1) of the code-dependent compensation cells are required maximally for k-th switching of the SAR ADC.

A rollable display device includes a rollable display and a first protection film disposed on a first surface of the rollable display. The first protection film extends beyond a first display edge of the rollable display. The rollable display device further includes a second protection film disposed on a second surface of the rollable display facing the first surface of the rollable display. The second protection film extends beyond the first display edge of the rollable display. The rollable display device additionally includes a first adhesive layer disposed between the rollable display and the first protection film. The rollable display device further includes second adhesive layer disposed between the rollable display and the second protection film, and a first adhesion part disposed adjacent to the first display edge of the rollable display and between the first protection film and the second protection film.

Comparators are implemented in many circuits, including analog-to-digital converters (ADCs). Some ADCs demand high bandwidth, low power consumption, and high speed. To address these requirements, a comparator circuit can be implemented without a separate pre-amplifier, where a sampling network drives a latch directly. Specifically, the comparator circuit integrates a pre-amplifier within the latch in a manner that ensures low power and high speed operation.

A voltage reference noise filter is provided that substantially eliminates noise with minimal external components for any circuit where the reference load current is a constant load and the circuit uses external components that have values that may vary with temperature, over time, and the like. The drift on an output of a voltage reference due to variation of resistor of the external filter is mitigated by moving the external resistor onto the chip containing the circuit. The voltage drop across the resistor is digitally compensated by a scaling factor determined during calibration. When more than one converter is provided on the chip, a further adjustment to the outputs of the converters is made based on the number of converters powered on or off. Also, error in output of converters due to mismatch among the converters is digitally compensated by a further scaling factor.

Comparators are implemented in many circuits, including analog-to-digital converters (ADCs). Some ADCs demand high bandwidth, low power consumption, and high speed. To address these requirements, a comparator circuit can be implemented without a separate pre-amplifier, where a sampling network drives a latch directly. Specifically, the comparator circuit integrates a pre-amplifier within the latch in a manner that ensures low power and high speed operation.

A solid-state imaging device includes: a pixel array unit in which a plurality of pixels are arranged in rows and columns; a plurality of column signal lines which are provided in one-to-one correspondence with pixel columns; a column processor including a plurality of column AD circuits provided in one-to-one correspondence with the plurality of column signal lines; a power supply variation detector which is connected to a power supply wire through which a power supply voltage is transmitted to each of the pixels, and which detects, in correspondence with pixel rows, power supply variation components attributed to variations in the power supply voltage; and a power supply variation corrector which corrects, for each of the pixel rows, a pixel signal detected by the column processor, using the power supply variation components detected by the power supply variation detector.