A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

A time-interleaved noise-shaping successive-approximation analog-to-digital converter (TI NS-SAR ADC) is shown. A first successive-approximation channel has a first set of successive-approximation registers, and a first coarse comparator operative to coarsely adjust the first set of successive-approximation registers. A second successive-approximation channel has a second set of successive-approximation registers, and a second coarse comparator operative to coarsely adjust the second set of successive-approximation registers. A fine comparator is provided to finely adjust the first set of successive-approximation registers and the second set of successive-approximation registers alternately. A noise-shaping circuit is provided to sample residues of the first and second successive-approximation channels for the fine comparator to finely adjust the first and second sets of successive-approximation registers.

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

An analog-to-digital converter, ADC, circuitry, comprises: an integrator connected to a capacitor, the integrator being configured to switch between integrating an analog input signal for ramping an integrator output and integrating a reference input signal for returning integrator output towards a threshold; a comparator for comparing integrator output to the threshold; and a timer for determining a time duration during which the reference input signal is integrated, the time duration providing a digital representation of an analog input signal value; the ADC circuitry further comprising a feedforward noise shaping loop configured to store a quantization error signal based on digitizing a first sample, the comparator being configured to receive a feedforward noise shaping signal for changing the threshold for digitizing a later sample of the analog input signal following the first sample.

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100 s of kHz (e.g., 200-300 kHz), or even higher.

A residue transfer loop, a successive approximation register analog-to-digital converter and a gain calibration method are disclosed. In particular, the residue transfer loop includes a sampling switch module, a logic controlling circuit, a residue holding capacitor module, a DAC capacitor array, a residue transfer module, a current rudder, a reset switch module and a charge sharing switch module. The logic controlling circuit sequentially outputs control signals according to preset time intervals in a preset period to control the reset switch module, the residue transfer module, the sampling switch module and the charge sharing switch module to work sequentially, thereby realizing a residue transfer.

An analogue-to-digital converter (ADC), comprising: an adaptive whitening filter configured to filter an analogue input signal and output a whitened analogue input signal; a first converter configured to receive said whitened analogue input signal and output a whitened digital signal; a controller configured to adapt the whitening filter based on the received analogue input signal.

An apparatus include one or more DACs and a resistor divider are configured to generate a variable bias voltage V.sub.BIAS with respect to a CM voltage V.sub.CM. The CM voltage V.sub.CM is applied to a cathode of one or more thermopiles or a negative input of one or more amplifiers to prevent saturation and over range of one or more low voltage readout amplifiers and one or more ADCs.

Disclosed are an analog-to-digital converter error shaping circuit and a successive approximation analog-to-digital converter. The analog-to-digital converter error shaping circuit includes a decentralized capacitor array, a data weighted average module, a mismatch error shaping module, a control logic generation circuit, a digital filter and a decimator. The decentralized capacitor array includes two symmetrically arranged capacitor array units, each capacitor array unit includes a first sub-capacitor array of a high segment bit and a second sub-capacitor array of a low segment bit. The data weighted average module is configured to eliminate correlation between the first sub-capacitor array and an input signal, and the mismatch error shaping module is configured to eliminate correlation between the second sub-capacitor array and the input signal.

A residue transfer loop, a successive approximation register analog-to-digital converter and a gain calibration method are disclosed. In particular, the residue transfer loop includes a sampling switch module, a logic controlling circuit, a residue holding capacitor module, a DAC capacitor array, a residue transfer module, a current rudder, a reset switch module and a charge sharing switch module. The logic controlling circuit sequentially outputs control signals according to preset time intervals in a preset period to control the reset switch module, the residue transfer module, the sampling switch module and the charge sharing switch module to work sequentially, thereby realizing a residue transfer.