A latched comparator comprises a pre-amplifier stage with a positive input (V.sub.in,p), a negative input (V.sub.in,n); and a differential output (V.sub.out) comprising a first output (V.sub.out,1) and a second output (V.sub.out,2), the pre-amplifier stage comprising a first cascode pair, comprising a first amplifying transistor (MN2) and a first cascode transistor (MN4) connected at a first cascode node, the first amplifying transistor (MN2) being controlled by the positive input (V.sub.in,p) and the first cascode transistor (MN4) being connected, opposite to the first cascode node, to the first output (V.sub.out,1); a second cascode pair, comprising a second amplifying transistor (MN3) and a second cascode transistor (MN5) connected at a second cascode node, the second amplifying transistor (MN3) being controlled by the negative input (V.sub.in,n) and the second cascode transistor (MN5) being connected, opposite to the second cascode node, to the second output (V.sub.out,2); a first gain-boosting transistor (MN6) connected between the first output (V.sub.out,1) and the first cascode node; and a second gain-boosting transistor (MN7) connected between the second output (V.sub.out,2) and the second cascode node, wherein the first gain-boosting transistor (MN6) and the second gain-boosting transistor (MN7) are cross-coupled, so that the first gain-boosting transistor (MN6) is controlled by the second output (V.sub.out,2) and the second gain-boosting transistor (MN7) is controlled by the first output (V.sub.out,2).

Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors; compare signals at outputs of the switched capacitors, each for a respective bit; sense whether a metastability condition exists for the comparator using the timer and setting a metastability flag upon each metastability detection for each bit; increase a value of the tunable time interval if more than one metastability flag is set during conversion of a sampled input signal; decrease a value of the tunable time interval if no metastability flags are set; and use the flags for a word completion in the cases when not all the bits have been evaluated.

A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.

Provided is a DA converter for outputting an analog signal according to an input digital signal, including a plurality of current output units to be input with the digital signal, which output a current according to the digital signal to a corresponding wiring, a conversion unit provided with a plurality of feedback paths respectively coupled to wirings corresponding to the current output units, and which selects at least one wiring among the wirings corresponding to the current output units and output an analog signal according to a current flowing in the selected wiring, and a first noise reduction unit provided with a plurality of first switches each of which switches whether to electrically connect to at least one wiring among the wirings corresponding to the current output units, and reduces a noise component generated in at least one of the plurality of current output units from the electrically coupled wiring.

Embodiments disclosed herein may reduce or even eliminate spurs introduced into the signals during analog to digital or digital to analog conversions. The spurs may be introduced by components such as clocks of the converter circuits. In an analog to digital conversion, the input signal may be split into two parts: the first portion passing through a first analog to digital converter (ADC) and an inverted second portion passing through a second ADC. A digital subtractor may subtract the output of the second ADC from the output of the first ADC converter thereby reducing the spurs. In digital to analog conversion, a digital input is passed through a first digital to analog converter (DAC) and an inverted digital input is passed through a second DAC. The output of the second DAC is inverted and combined with the output of the first DAC to reduce the spurs.

A digital-to-analog converter (DAC)-based voltage-mode transmit driver architecture. One example transmit driver circuit generally includes an impedance control circuit coupled to a plurality of DAC driver slices. The impedance control circuit generally includes a tunable impedance configured to be adjusted to match a load impedance for the transmit driver circuit. Another example transmit driver circuit generally has an output impedance that is smaller than the load impedance for the transmit driver circuit, such that an output voltage swing at differential output nodes of the transmit driver circuit is greater than a voltage of a power supply rail. Another example transmit driver circuit generally includes a predriver circuit with a first inverter coupled to a first output of the predriver circuit and a second inverter coupled to a second output of the predriver circuit, the transistors in at least one of the first inverter or the second inverter having different strengths.

An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.

Systems and methods are provided for improved linearity of audio amplifiers. In one example, a system includes a first current source configured to provide a first current signal having a first current source output capacitance, and a second current source configured to provide a second current signal having a second current source output capacitance, where the first and second current source output capacitances are a different value. The system further includes a first capacitor compensation device coupled to an output of the first current source configured to provide a capacitance value to compensate for the second current source output capacitance, and a second capacitor compensation device coupled to an output of the second current source configured to provide a capacitance value to compensate for the first current source output capacitance. The system further includes a plurality of switches configured to switch the first and second current signals.

Comparison circuitry includes a comparator having a first input configured to receive a pixel signal. A switch is coupled to a second input of the comparator, a reference generator, and a ramp generator. A first capacitance is coupled to the switch. The switch is configured to couple the first capacitance to the reference generator to charge the first capacitance to a reference voltage from the reference generator prior to a ramp event in a ramp signal, and to couple the first capacitance to the ramp signal from the ramp generator at an onset of the ramp event in the ramp signal. The first capacitance is coupled to provide positive current injection into the ramp signal at the onset of the ramp event in the ramp signal to reduce a ramp settling time in the ramp signal, which is provided to the second input of the comparator.

An electronic system includes a digital-to-analog converter (DAC) circuit to provide a drive signal to a second circuit that provides a system output, and a control circuit connected to an input of the DAC circuit. The control circuit is configured to receive a target signal at an input of the control circuit, provide a control circuit output to the input of the DAC circuit according to the target signal, detect when a transition of the DAC circuit results in a glitch signal at an output of the DAC circuit, and provide a compensation signal to the DAC circuit to reduce a magnitude of the glitch signal.