A digital-to-analog converter comprises a plurality of first digital-to-analog converter cells configured to generate a first analog signal based on first digital data, wherein the first digital-to-analog converter cells of the plurality of first digital-to-analog converter cells are coupled to a first output node for coupling to a first load. Further, the digital-to-analog converter comprises a plurality of second digital-to-analog converter cells configured to generate one or more second analog signals based on second digital data, wherein the second digital-to-analog converter cells of the plurality of second digital-to-analog converter cells are coupled to one or more second output nodes, and wherein the plurality of first digital-to-analog converter cells and the plurality of second digital-to-analog converter cells are coupled to a power supply node for coupling to a mutual power supply.

The present invention provides a reference voltage generating circuit. The reference voltage generating circuit includes a charge supply circuit providing a first reference voltage during a first period; and a voltage supply circuit providing a second reference voltage during a second period. The voltage supply circuit does not provide the second reference voltage during the first period.

An analog-to-digital conversion device of the embodiment includes a comparator and a logic circuit including a switch unit and a logic gate unit that receives a signal output from a comparator. The logic gate unit and the switch unit are connected to each other in series between a power supply node and a ground node.

A circuit includes an analog-to-digital converter (ADC) and a hysteresis circuit. The ADC is configured to generate a series of digital codes. The hysteresis circuit is configured to: (a) determine that a first digital code of the series of digital codes represents a change in a same direction as previous digital codes and store the first digital code in the register; and (b) determine that a second digital code of the series of digital codes represents a change in direction from previous digital codes, determine that the second digital code is less than a hysteresis value different than a preceding digital code, and not store the second digital code in the register.

Single-stage and multiple-stage current-mode Analog-to-Digital converters (iADC)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed iADCs can operate asynchronously and be free from the digital clock noise, which also lowers dynamic power consumption, and reduces circuitry overhead associated with free running clocks. For their pseudo-flash operations, the disclosed iADCs do not require their input current signals to be replicated which saves area, lowers power consumption, and improves accuracy. Moreover, the disclosed methods of multi-staging of iADCs increase their resolutions while keeping current consumption and die size (cost) low. The iADC's asynchronous topology facilitates decoupling analog-computations from digital-computations, which helps reduce glitch, and facilitates gradual degradation (instead of an abrupt drop) of iADC's accuracy with increased input current signal frequency. The iADCs can be arranged with minimal digital circuitry (i.e., be digital-light), thereby saving on die size and dynamic power consumption.

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

A digital-to-analog converter (DAC) capable of operating in radio frequency (RF) with linear output, low distortion, low power consumption, and input data independence. The DAC includes switch drivers and output switches driven by the switch drivers. The switch drivers include pairs of outputs, and positive feedback circuitries coupled between respective pairs of outputs. The output switches are arranged between a first current source configured to push current to the DAC's outputs and a second current source configured to pull current from the DAC's outputs. Different output switches are configured to push current to and pull current from the DAC's outputs in accordance with rising edges and falling edges, respectively.

A dynamic error introduced by track-and-hold circuits can be reduced by using an input signal derivative to perform linear extrapolation during the hold period, allowing the output of the track-and-hold circuit to provide improved performance in reconstructing an undistorted input waveform, or to perform other applications such as demultiplexing. As described herein, a track-and-hold circuit and related techniques can include use of a first-order (e.g., linear) extrapolation. A first-order extrapolation can better approximate or reconstruct a signal during a specified hold duration, as compared to a zeroth-order technique. Use of analog circuits to implement the first-order extrapolation can one or more of reduce complexity of a circuit implementation or improve performance, such as by not requiring digital signal processing circuitry in performing the extrapolation.

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors; compare signals at outputs of the switched capacitors, each for a respective bit; sense whether a metastability condition exists for the comparator using the timer and setting a metastability flag upon each metastability detection for each bit; increase a value of the tunable time interval if more than one metastability flag is set during conversion of a sampled input signal; decrease a value of the tunable time interval if no metastability flags are set; and use the flags for a word completion in the cases when not all the bits have been evaluated.