A digital microphone includes a first modulation path having an input for receiving an analog input signal and an output for generating a first digital signal; a second modulation path having an input for receiving the analog input signal and an output for generating a second digital signal; a summing circuit having a first input for receiving the first digital signal, a second input for receiving the second digital signal, and an output for generating a digital calibration path signal; and a difference circuit having a first input for receiving the first digital signal, a second input for receiving the second digital signal, and an output for generating a digital signal path signal.

An analog-to-digital converter, ADC, is provided. The ADC comprises multiple time-interleaved sub-ADCs, a detection circuit, and a calibration circuit. The sub-ADCs are configured to, when the ADC is in a calibration mode, generate a first signal by sampling a calibration signal based on a first clock signal and at least a second clock signal. The first clock signal comprises a phase shift relative to the second clock signal. The calibration circuit is configured to determine a first mismatch between the phase shift and a phase shift threshold based on the first signal. The detection circuit is configured to, when the ADC is in an operation mode, generate a second signal by sampling one of a biased signal to be received by the sub-ADCs or a second calibration signal based on at least one of the first clock signal and the second clock signal. The calibration circuit is configured to determine a second mismatch between the phase shift and the phase shift threshold based on the second signal and calibrate the ADC based on the first and the second mismatch.

A method for predictive level-crossing, LC, in an analog-to-digital converter, ADC, is provided. The method comprises the steps of comparing a first input signal sampled during a first sampling period with one of an upper threshold level and a lower threshold level to determine if a level crossing has occurred during said first sampling period. Which one of said two threshold levels that is compared with said first input signal is based on if a level crossing occurred during a prior sampling period directly prior to the first sampling period, and which one of the two threshold levels was compared to a prior input signal sampled during said prior sampling period.

Analog-to-digital converters (ADCs) with background calibration processes are disclosed. In one aspect, an ADC with a plurality of comparators that each compare an input voltage to voltages that are generated at taps across a plurality of references (e.g., a reference resistor ladder). The comparators are initially calibrated with foreground calibration routines and continuously recalibrated to compensate for aging, voltage, and temperature variations without interrupting operation of the ADC by randomly taking one comparator of the plurality of comparators off-line to run calibration processes without replacing that comparator. The value for the off-line comparator may be reliably inferred from values from neighboring comparators or, in some cases, guessed randomly. While possible errors may be introduced, such errors may be driven to a mean square quantization noise level through exemplary aspects of the present disclosure.

Systems and methods are related to device including but not limited to a SAR ADC. The device includes a first digital to analog conversion (DAC) circuit including first capacitors. The digital to analog conversion (DAC) circuit is configured to adjust a first input voltage in response to a first control signal. The device also includes a first comparator configured to receive an adjusted input voltage from the digital to analog conversion (DAC) circuit. The first control signal is provided in response to a target input voltage and a sensed input voltage and adjusts the first input voltage using the first capacitors.

A delay-domain analog-to-digital converter (ADC) including first and second ADCs and corresponding look-up table (LUT) memories. Control logic controls the first ADC to convert a first analog level plus a first offset to a first digital value; controls the second ADC to convert the first analog level plus a second offset to a second digital value; and computes a first difference value between the first and second digital values. The control logic further controls the first ADC to convert the first analog level minus the first offset to a third digital value; controls the second ADC to convert the first analog level plus the second offset to a fourth digital value; computes a second difference value between the third and fourth digital values; and adjusts a correction value for the first analog level in the LUT memory based on a third difference between the first and second difference values.

Systems and methods for providing multiple stable reference voltages are disclosed. In one aspect, a bandgap reference circuit generates a first reference voltage, which is calibrated with an adjustable resistor bank. Settings for this adjustable resistor bank may be stored in a memory and reused at multiple locations with theoretically identical resistor banks for other circuits requiring reference voltages. Recognizing that there may be voltage network variations induced by distances from bandgap reference circuit, process variations between resistor banks, or the like, each resistor bank may be separately calibrated, and settings stored in memory. By providing separate resistor banks for each location that needs a reference voltage, the need for duplicative and space intensive bandgap reference circuits is minimized. Further, by providing separate resistor banks, variations in the local voltage are minimized providing more stable and reliable operation of circuits in the die.

A circuit includes a switched capacitor amplifier circuit, a multi-bit quantizer circuit, an accumulator circuit, a cyclic result register, and a result combination circuit. The switched capacitor amplifier circuit has an output. The multi-bit quantizer circuit has an input coupled to the output of the switched capacitor amplifier circuit, and an output. The accumulator circuit has an input coupled to the output of the multi-bit quantizer circuit, and an output. The cyclic result register has an input couped to the output of the multi-bit quantizer, and an output. The result combination circuit has a first input coupled to the output of the accumulator circuit, and a second input coupled to the output of the cyclic result register.

An ADC circuit including: ADCs to perform conversion operations in a time-interleaving manner; and a control logic circuit connected to the ADCs, wherein the control logic circuit is configured to: calculate a correlation value between data output from the ADCs a first number of times using a first number of bits among each bit of the data; calibrate a sampling timing of at least some of the ADCs, based on a first cumulative correlation value, which is obtained by accumulating correlation values calculated the first number of times; calculate the correlation value between the data a second number of times by using a second number of bits in each of the data; and calibrate the sampling timing of the at least some of the ADCs, based on a second cumulative correlation value, which is obtained by accumulating correlation values calculated the second number of times.

A test and measurement instrument includes one or more channels to receive a signal under test, each channel comprising an input port, a filter, and a sampler, at least one analog-to-digital converter (ADC), the at least one ADC having two pipes connected to the sampler of one of the one or more channels, the at least one ADC to produce digital samples of the signal at a sample rate, and one or more processors configured to execute code that causes the one more processors to acquire a spectrum of the digital samples for each pipe in the at least one ADC, and use the spectrums of the digital samples for each pipe in the at least one ADC to reconstruct the spectrum of the signal under test. A method of operating a test and measurement instrument, and a method a method of calibrating a test and measurement instrument is included.