A high-speed data receiver includes interleaver circuitry configured to divide a received data stream into a plurality of interleaved paths for processing, spectral content detection circuitry configured to derive spectral content information from data on each of the plurality of interleaved paths, sorting circuitry configured to bin the derived spectral content information according to energy levels, stream attribute determination circuitry configured to determine, based on sorted spectral content, one or more of path offsets of the interleaved paths, gain mismatch among interleaved paths, signal bandwidth mismatch and pulse width mismatch, and equalization circuitry configured to correct the one or more of the determined offsets, the determined gain mismatch and the determined signal width mismatch. Equalization circuitry may be configured to equalize a gain-normalized signal by separately adjusting respective bandwidth actuators of each respective interleaved path and respective pulse width actuators of each respective interleaved path.

A measuring amplifier (103) with background calibration and adjustment amplifies, digitizes and processes at least one measurement signal (111) from at least one measuring transducer (102) with the aid of at least one amplifier arrangement (108). This can be intermittently replaced by an additional amplifier arrangement (107), which enables interruption-free direct calibration and, if necessary, adjustment of the amplifier arrangement. In the calibration, both a zero point error and an amplification error of the amplifier arrangement are reliably determined. A high accuracy is achieved without measurement interruption. Only one additional amplifier arrangement is generally required, even for a measuring amplifier with plural channels.

Approaches provide for calibrating high speed analog-to-digital converters (ADCs). For example, a calibration signal can be applied to parallel ADCs. The output of the parallel ADCs can be analyzed using a set of filtering components configured to at least filter image components and cause a phase shift in the output signals. One or more delay adjustment components can cause a delay to at least the output of the parallel ADCs and the set of filtering components. A cross-correlating component can be utilized to cross-correlate the output of the parallel ADCs with an output signal of at least one filtering component of the set of filtering components and an output signal of at least one delay adjustment component of the set of delay adjustment components. A conversion component determines polar coordinates from rectangular coordinates from the output of the cross-correlating component. Thereafter, a time-offset and gain estimator component can determine one of gain error calibration data or time-offset calibration data based at least in part on an output signal of the conversion component, which can be stored and/or used to calibrate individual time-interleaved ADCs.

A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460). The DAC (430) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller (418) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC (430) and the digital signal reconstruction circuit (450) to implement a small signal mapping mode of operation.

The present invention provides a device and method for correcting error estimation of an analog-to-digital converter. The method comprises: according to a preset initial value of a correction parameter, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to the initial value of a correction parameter, correcting a gain error between channels, generating a general correction signal, buffering the general correction signal and triggering a counting cell to start counting, and meanwhile calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting up to a preset value, setting enable ends of a low-pass filter accumulating cell and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching the error estimation result, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching the updated clock correction parameter and gain correction parameter, and resetting to carry out cyclic estimation correction. According to the present invention, in the case where a few effective sample points are used, the estimation accuracy is improved and the convergence rate of the estimation correction is increased.

An example time-skew calibration circuit includes a plurality of first circuits, each including a first accumulator and a second accumulator. The time-skew calibration circuit further includes a plurality of second circuits, each including a first adder coupled to outputs of the first accumulator and the second accumulator, and a first subtractor coupled to the outputs of the first accumulator and the second accumulator. The time-skew calibration circuit further includes a decision circuit configured to combine an output of the first adder and an output of the first subtractor.

Multi-step ADCs performs multi-step conversion by generating a residue for a subsequent stage to digitize. To generate a residue, a stage in the multi-step ADC would reconstruct the input signal to the stage using a feedforward digital to analog converter (DAC). Non-linearities in the DAC can directly affect the overall performance of the multi-step ADC. To reduce power consumption and complexity of analog circuit design, digital background calibration schemes are implemented to address the non-linearities. The non-linearities that the calibration schemes address can include reference, DAC, and quantization non-linearities.

A semiconductor device, a signal processing system, and a signal processing method are provided that regulate a change of characteristics in the event of aged deterioration. The semiconductor device of the present invention includes a reference voltage generation circuit that generates a reference voltage, an analog signal processing circuit that outputs a first processing signal according to the reference voltage, a test signal output section that outputs, as a test signal, a second processing signal having a lower voltage than the first processing signal, an input section that receives a regulation signal for the outputted test signal, and a regulator circuit that regulates the output of the analog signal processing circuit in response to the regulation signal.

An apparatus is provided which comprises: a thermal sensor comprising one or more n-type devices or p-type devices that suffer from subthreshold factor variation, wherein the thermal sensor is to generate an output digital code representing a temperature; and a calibration circuitry coupled to the thermal sensor, wherein the calibration circuitry is to trim the effects of subthreshold factor variation from the output digital code.

An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M1 sampling phases of the M sampling phases. The phase control circuit comprises M1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.