A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.

There provided an AD converter that includes an analog processing part configured to select one of the measurement target voltages and a plurality of reference voltages for each channel, to output an analog voltage signal; a first selection part configured to select one of a plurality of analog voltage signals; a first AD conversion part configured to perform AD conversion on the analog voltage signal to generate a first original digital signal; a second selection part configured to select one of the plurality of analog voltage signals; a second AD conversion part configured to perform AD conversion on the analog voltage signal to generate a second original digital signal; a digital processing part configured to receive the first original digital signal and the second original digital signal; and a controller configured to control contents selected in the analog processing part, the first selection part, and the second selection part.

An apparatus for determining one or more calibration values of an ADC is configured to receive a first reference signal and a second reference signal and apply to the ADC the following: over a first signal application period, a first ADC input signal including the first reference signal; over a second signal application period, a second ADC input signal having a substantially equal magnitude and an inverse polarity to the first ADC input signal; over a third signal application period, a third ADC input signal including the second reference signal; and over a fourth signal application period, a fourth ADC input signal having a substantially equal magnitude and an inverse polarity to the third ADC input signal. The apparatus is configured to determine the one or more calibration values based, at least in part, on an ADC output signal of the ADC over the four signal application periods.

Various embodiments of a segmented R-DAC are disclosed. In one embodiment, a segmented R-DAC includes first and second DACs arranged to receive most and least significant bits, respectively. The segmented R-DAC also includes a first capacitor coupled between an output of the first DAC and an output of the second DAC, and a second capacitor coupled between the output of the second DAC and a ground node. The capacitance of the second capacitor has a value that is a predetermined multiple of the capacitance value of the first capacitor.

A method of tuning a production module using a reference module with virtual gain correction is provided. The method includes selecting a counterpart reference module created for a select application. The production module is commutatively coupled to the selected counterpart reference module to generate a production module pair. A production module gain curve for the production module pair is measured for each frequency band to be used by the production module. The production module is tuned based at least in part on offset gain values at select number of frequency observation points for each frequency band associated with the counterpart reference module and gain values at the select number of frequency observation points of the measured production module gain curve for each frequency band.

Random chopping is an effective technique for data converters. Random chopping can calibrate offset errors, calibrate offset mismatch in interleaved ADCs, and dither even order harmonics. However, the non-idealities of the (analog) chopper circuit can limit its effectiveness. If left uncorrected, these non-idealities cause severe degradation in the noise floor that defeats the purpose of chopping, and the non-idealities may be substantially worse than the non-idealities that chopping is meant to fix. To address the non-idealities of the random chopper, calibration techniques can be applied, using correlators and calibrations that may already be present for the data converter. Therefore, the cost and digital overhead are negligible. Calibrating the chopper circuit can make the chopping more effective, while relaxing the design constraints imposed on the analog circuitry.

An electronic device is disclosed that includes an analog-to-digital converter circuit, an adaptive filter circuit coupled to the analog-to-digital converter circuit to correct one or more circuit impairments in the analog-to-digital converter circuit, a training signal generator circuit to generate training signals, and an amplitude detector circuit configured to suspend generation of the training signals and cause the adaptive filter circuit to suspend adaptation when the input signal is above a predetermined threshold.

There provided an AD converter that includes an analog processing part configured to select one of the measurement target voltages and a plurality of reference voltages for each channel, to output an analog voltage signal; a first selection part configured to select one of a plurality of analog voltage signals; a first AD conversion part configured to perform AD conversion on the analog voltage signal to generate a first original digital signal; a second selection part configured to select one of the plurality of analog voltage signals; a second AD conversion part configured to perform AD conversion on the analog voltage signal to generate a second original digital signal; a digital processing part configured to receive the first original digital signal and the second original digital signal; and a controller configured to control contents selected in the analog processing part, the first selection part, and the second selection part.

Multi-step ADCs performs multi-step conversion by generating a residue for a subsequent stage to digitize. To generate a residue, a stage in the multi-step ADC would reconstruct the input signal to the stage using a feedforward digital to analog converter (DAC). Non-linearities in the DAC can directly affect the overall performance of the multi-step ADC. To reduce power consumption and complexity of analog circuit design, digital background calibration schemes are implemented to address the non-linearities. The non-linearities that the calibration schemes address can include reference, DAC, and quantization non-linearities.

An analog-to-digital converter (ADC) circuit (400) and method of operation are disclosed. In some aspects, the ADC circuit (400) may include a plurality of channels (500), a gain calibration circuit (420), and a time-skew calibration circuit (430). Each of the plurality of channels (500) may include an ADC (520), a switch (510) configured to provide a differential input signal to the ADC (520), a calibration device (530), a multiplier (540), and a pseudorandom bit sequence (PRBS) circuit (550) to provide a pseudorandom number (PN) to the switch (510), to the calibration device (530), and to the multiplier (540). In some embodiments, the calibration device (530) may include first and second offset calibration circuits (531-532) coupled in parallel between a de-multiplexer (D1) and a multiplexer (M1) that alternately route signals to the first and second offset calibration circuits (531-532) based on the pseudorandom number (PN).