An analog to digital converter device includes a capacitor array, a digital logic circuit, and a comparator circuit. The capacitor array includes first capacitors, a capacitor to be calibrated, and compensation capacitors. The digital logic circuit performs a calibration on the capacitor to be calibrated, in order to calibrate a weighed value of the capacitor to be calibrated according to a decision signal, and converts an input signal to bits via the capacitor array after the calibration is performed. The comparator circuit compares a testing signal with a predetermined voltage to generate the decision signal. The testing signal is generated by the first capacitors and the capacitor to be calibrated in response to the calibration. The digital logic circuit further selects at least one of the compensation capacitors, in order to adjust a digital code corresponding to a calibrated weighed value to be an integer expressed by the bits.

An apparatus is provided to calibrate an analog-to-digital converter (ADC). The apparatus includes a calibration circuitry coupled to an output of the ADC, wherein the calibration circuitry is to identify a maximum value and minimum value of the output of the ADC, and is to calibrate one or more performance parameters of the ADC according to the maximum and minimum values. The performance parameters include: gain of the ADC, offset of the ADC, and timing skew between the ADC and a neighboring ADC.

Various embodiments of the present technology may provide methods and apparatus for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC may provide a first digital calibration circuit configured to correct systemic mismatch and a second digital calibration circuit configured to correct random mismatch. Together, the first and second digital calibration circuits resolve missing codes in the SAR ADC output.

A method is described that is performed by a calibration system. The method includes determining a set of perturbation values for configuring an analog-to-digital converter of the calibration system; generating a set of digital test values for determining the accuracy of the analog-to-digital converter; and applying the set of perturbation values to the set of digital test values to generate a set of modified test values, wherein the set of perturbation values are digital values that are applied to the set of digital test values in the digital domain.

The invention discloses a calibration circuit and a calibration method for an analog-to-digital converter (ADC). The calibration method of the ADC includes the following steps: (a) resetting the voltage at the first input of the comparator and the voltage at the second input of the comparator; (b) changing a terminal voltage of at least one capacitor in the first capacitor group; (c) the ADC generating a first digital code; (d) after the first digital code is obtained, resetting the voltage at the first input of the comparator and the voltage at the second input of the comparator; (e) changing a terminal voltage of at least one capacitor in the third capacitor group; and (f) the ADC generating a second digital code. The first digital code and the second digital code are used to correct the output of the ADC.

Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.

An apparatus for calibrating a time-interleaved analog-to-digital converter including a plurality of time-interleaved analog-to-digital converter circuits is provided. The apparatus includes a clock generation circuit configured to generate a plurality of phase shifted clock signals for the plurality of time-interleaved analog-to-digital converter circuits and a reference clock signal. Further, the apparatus includes a reference signal generation circuit configured to generate a reference signal based on the reference clock signal. The reference signal is a square wave signal. The apparatus additionally includes a coupling circuit configured to controllably couple an input node of the time-interleaved analog-to-digital converter to either the reference signal generation circuit or to a signal node capable of providing an analog signal for digitization.

The invention discloses a calibration circuit and a calibration method for an analog-to-digital converter (ADC). The calibration method of the ADC includes the following steps: (a) resetting the voltage at the first input of the comparator and the voltage at the second input of the comparator; (b) changing a terminal voltage of at least one capacitor in the first capacitor group; (c) the ADC generating a first digital code; (d) after the first digital code is obtained, resetting the voltage at the first input of the comparator and the voltage at the second input of the comparator; (e) changing a terminal voltage of at least one capacitor in the third capacitor group; and (f) the ADC generating a second digital code. The first digital code and the second digital code are used to correct the output of the ADC.

Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.

VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC.