Aspects of the present disclosure provide techniques and apparatus for distributed built-in self-test. An example method of testing circuitry includes testing, in a first occasion, a first electrical circuit, having a first component, using at least a second component of a second electrical circuit; and testing, in a second occasion, the second electrical circuit using at least the first component of the first electrical circuit.

A first mode in which to output analog electricity quantities of objects one by one independently to an A/D converter, a second mode in which to output none of the analog electricity quantities of the objects, a third mode in which to output none of the analog electricity quantities of the objects and cause the output to the A/D converter to be resistor, and a fourth mode in which to output to the A/D converter a plurality of the analog electricity quantities of the objects at the same time, are caused to be generated, thus acquiring the A/D conversion values of the objects individually when in the first mode, and detecting an anomaly of the A/D converter itself or a device connected to the A/D converter when in the second mode to the fourth mode.

Methods are provided for supervising a motor control unit with at least two separate channels, each of the two channels including at least: means for executing a given application task AS, the application task AS including a plurality of successively executed computations between which latency periods elapse; a first component capable of performing the computations; a second component capable of storing data; the application tasks AS of the channels being capable of communicating. The method includes the following steps: a) detecting a latency period; b) performing, during this latency period, an operating state test of at least one of the components; and c) determining a state of the component corresponding to a failure state or a healthy state.

An analog-to-digital converter including a converter arrangement configured to provide a digital output signal as an output of the analog-to-digital converter based on an analog input signal comprising an input to the analog-to-digital converter, the analog-to-digital converter including a calibration module configured to provide calibration signalling to set one or more of a gain of one or more components of the converter arrangement and an offset of one or more components of the converter arrangement, the calibration module further configured to provide, as an output, diagnostic information based on the calibration signalling for use in determining the occurrence of a fault in the analog-to-digital converter.

An analog-to-digital converter including a converter arrangement configured to provide a digital output signal as an output of the analog-to-digital converter based on an analog input signal comprising an input to the analog-to-digital converter, the analog-to-digital converter including a calibration module configured to provide calibration signalling to set one or more of a gain of one or more components of the converter arrangement and an offset of one or more components of the converter arrangement, the calibration module further configured to provide, as an output, diagnostic information based on the calibration signalling for use in determining the occurrence of a fault in the analog-to-digital converter.

The present disclosure describes a channel selector for use in an analog-to-digital converter that has a sampling circuit for converting an analog input to a digital output within a fault tolerance range. The channel selector includes a reception channel, a diagnostic channel, and an impedance compensator. The reception channel receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel receives a diagnostic signal for verifying the digital output of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator is configured to offset a high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.

The present disclosure provides systems and methods for identifying and reporting failures of an analog to digital (A/D) conversion system. The systems and methods are configured to detect and report a failure of a preamplifier of the A/D conversion system and/or a failure of a A/D converter of the A/D conversion system. A high frequency component can be included in the input of an A/D converter. The A/D converter is configured to output a digital value to the A/D conversion system, wherein the digital value includes the high frequency component of the A/D converter input. The A/D conversion system is configured to determine an output status, including a frequency component and a corresponding amplitude, and to determine a failure of the A/D conversion system based on the determined output status. The A/D conversion system can report a change in, or a failure of, the A/D converter, and can operate or prevent operation of protection elements.

The present disclosure provides systems and methods for identifying failures in an analog to digital (A/D) converter. An intelligent electronic device (IED) may monitor a digital output of one or more A/D converters. The IED may determine a slope value limit associated with the A/D converter. The IED may determine an output slope value of the digital output based on a difference of a converter output value measured at a first time and a converter output value measured at a later time. If the determined output slope value exceeds the slope value limit, the IED may identify a failure of the A/D converter. An IED may determine that concurrent failures in multiple, parallel A/D converters are indicative of a problem upstream from the A/D converters.

There is disclosed herein analogue-to-digital converter circuitry, comprising a set of sub-ADC units each for carrying out analogue-to-digital conversion operations, the set comprising a given number of core sub-ADC units for carrying out said given number of core conversion operations. Also provided is control circuitry operable, when a said sub-ADC unit is determined to be a defective sub-ADC unit, to cause the core conversion operations to be carried by the sub-ADC units of the set sub-ADC units other than the defective sub-ADC unit.

A sensor system (1, 1S) including a current DA converter (42) outputting a control current (Ip) of a sensor element (3S), a control unit (4C) generating a control current instruction value (Ipcmd) corresponding to magnitude of the control current and inputting this instruction value to the current DAC, an instruction value sequence generating unit (47) generating, instead of the control current instruction value, an inspection instruction value sequence (RChcmd) in which predetermined inspection current instruction values (Chcmd) inputted to the current DAC are arranged in order and by which failure of the current DAC can be detected, an inspection current detection unit (71) detecting an inspection current value (Ichv) of an inspection current (Ich) outputted from the current DAC, and a failure detection unit (8) detecting failure of the current DAC from an inspection current value sequence (RIchv) in which the inspection current values are arranged in order of detection.