The present invention provides a semiconductor device and a failure detection method capable of detecting an excessive variation among elements that constitute an analog circuit as a failure. According to an embodiment, a semiconductor device 1 includes: an AD converter 11; a digital assist circuit 12 that corrects an error of a digital signal Do corresponding to an analog signal Ain processed by the AD converter 11; and a failure detection circuit 13 that detects whether the AD converter 11 has a failure based on a correction amount by the digital assist circuit. The semiconductor device 1 is therefore able to detect the excessive variation among the elements that constitute the AD converter 11 as a failure.

The present disclosure provides systems and methods for identifying failures in an analog to digital (A/D) converter. An intelligent electronic device (IED) may monitor a digital output of one or more A/D converters. The IED may determine a slope value limit associated with the A/D converter. The IED may determine an output slope value of the digital output based on a difference of a converter output value measured at a first time and a converter output value measured at a later time. If the determined output slope value exceeds the slope value limit, the IED may identify a failure of the A/D converter. An IED may determine that concurrent failures in multiple, parallel A/D converters are indicative of a problem upstream from the A/D converters.

A method for calibrating an analog-to-digital converter includes the following steps: conducting an initial performance test and judgement on the analog-to-digital converter; if the initial performance test succeeds, performing a pre-trimming and judgement on the analog-to-digital converter; if the pre-trimming succeeds, performing an error extraction on the analog-to-digital converter, obtaining errors of conversion stages of the analog-to-digital converter; performing an error soft trimming and test on the analog-to-digital converter according to the errors of the conversion stages; and if the error soft trimming and test of the analog-to-digital converter succeed, performing an error hard trimming and test on the analog-to-digital converter according to the errors of the conversion stages.