A constant current source, a stable time base and a capacitor are used to self-check operation of an analog-to-digital convertor (ADC) by charging the capacitor for a pre-determined amount of time to produce a voltage thereon. This voltage will be proportional to the amount of time that the capacitor was charged. Multiple points on the ADC transfer function can be verified in this self-check procedure simply by varying the amount of time for charging of the capacitor. Relative accuracy among test points may then be easily obtained. Absolute accuracy may be obtained by using an accurate clock reference for the time base, a known current source and capacitor value.

An ADC calibration system includes a clock generating circuit, under test ADCs, a standard ADC, and a calibration circuit. The clock generating circuit generates operation clocks according to a system clock, and generates a calibration clock according to the system clock and a selection signal. The under test ADCs sample an input signal according to the operation clocks to output under test sampling results. The standard ADC samples the input signal according to the calibration clock to output a standard sampling result. The calibration circuit makes the phases of the calibration clock and a first operation clock received by a first ADC to be the same. The calibration circuit compares the standard sampling result with a first under test sampling result to generate calibration information corresponding to the first under test sampling result, and calibrates the first under test sampling result according to the calibration information.

A switching digital-to-analog converter (DAC) includes a logic gate for receiving a digital input signal having rising and falling edges defining an input pulse width, and outputting an offset input signal having rising and falling edges defining a mismatched pulse width different from the input pulse width due to relative movement of the rising and falling edges in response to a voltage offset introduced by the logic gate. A DC voltage source provides a direct current (DC) calibration signal, and a summer adds the DC calibration signal and the offset input signal to compensate for the voltage offset introduced by the logic gate, and to provide a corrected input signal. A unit DAC receives the corrected input signal, and selectively switches current to an output of the switching DAC in response to voltage values of the corrected input signal to provide an analog output.

Representative implementations of devices and techniques provide a built-in self-test (BIST) for an analog-to-digital converter (ADC). Stimuli needed to test an ADC are generated within the chip containing the ADC. Evaluation circuitry is also available on-chip. Generation and evaluation circuits and systems are based on existing circuits and/or components of the chip.

Representative implementations of devices and techniques provide a built-in self-test (BIST) for an analog-to-digital converter (ADC). Stimuli needed to test an ADC are generated within the chip containing the ADC. Evaluation circuitry is also available on-chip. Generation and evaluation circuits and systems are based on existing circuits and/or components of the chip.

The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

Disclosed are systems and methods for identifying and reporting failures of an analog-to-digital converter (ADC). Specifically, the systems and methods described herein evaluate quantization noise properties of ADCs, including delta-sigma ADCs and successive approximation register (SAR) ADCs, to verify functionality and/or identify failures. Quantization noise properties can be evaluated in the frequency domain by, for example, comparing RMS values, magnitudes, frequency spectrums, and the like, in various frequency bands to threshold values and/or to verify an expected noise shape. Quantization noise properties can additionally or alternatively be evaluated in the time domain by, for example, comparing counts of pulse widths, average pulse widths, and/or number of transitions within a sequence of pulses to threshold values and/or to similar identifiable characteristics in other pulse width bands.

Many systems implement calibration schemes to measure and correct for the non-idealities. Such systems can be complex, which makes them impractical to implement since the cost can potentially outweigh the benefits of the calibration scheme. To implement efficient and effective calibration, non-idealities or errors of a system are detected, in foreground or in background, in a piecewise fashion based on, e.g., correlations of an output signal with an uncorrelated random signal, where the correlation results are processed separately for different open intervals of an error signal. Second order and third order correction terms can be easily determined based on three open intervals. In various embodiments, the calibration scheme can detect and correct for linear errors, (linear and non-linear) memory/frequency dependent errors, static nonlinearity errors, Hammerstein-style non-linearity errors, and Wiener-style non-linearity errors (cross-terms).

Many systems implement calibration schemes to measure and correct for the non-idealities. Such systems can be complex, which makes them impractical to implement since the cost can potentially outweigh the benefits of the calibration scheme. To implement efficient and effective calibration, non-idealities or errors of a system are detected, in foreground or in background, in a piecewise fashion based on, e.g., correlations of an output signal with an uncorrelated random signal, where the correlation results are processed separately for different open intervals of an error signal. Second order and third order correction terms can be easily determined based on three open intervals. In various embodiments, the calibration scheme can detect and correct for linear errors, (linear and non-linear) memory/frequency dependent errors, static nonlinearity errors, Hammerstein-style non-linearity errors, and Wiener-style non-linearity errors (cross-terms).

An ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.