Systems and methods for measuring and compensating a DC-transfer characteristic of analog-to-digital converters are described. A test-signal generator comprising a sigma-delta modulator may provide calibration signals to an ADC. An output from the ADC may be filtered with a notch filter to suppress quantization noise at discrete frequencies introduced by the sigma-delta modulator. The resulting filtered signal may be compared against an input digital signal to the test-signal generator to determine a transfer characteristic of the ADC.

A digital to analog converter (DAC) maps a digital word to an analog output. The DAC bits may have amplitude and timing errors. These errors (or sometimes referred herein as non-idealities) result in distortion and degradation of the dynamic range in DACs. To reduce these negative effects, delta-sigma patterns can be provided to two bit cells, a reference bit cell and a bit cell under calibration, to perform, e.g., amplitude calibration and timing skew calibration. Delta-sigma patterns are particularly advantageous over square wave signals, which cannot be scaled to perform amplitude calibration between bit cells having different bit weights and are limited in frequency to integer fractions of the sampling clock.

The present disclosure provides systems and methods for identifying changes in and failures of a reference voltage of an analog to digital (A/D) converter. A non-scalar function of the reference voltage of the A/D converter can be determined and output to the A/D converter. The A/D converter is configured to output a digital value to the A/D conversion system, wherein the digital value corresponds to the non-scalar function of the reference voltage. The A/D conversion system decodes the non-scalar function of the reference voltage with a corresponding inverse function, and may determine the drift factor associated with the reference voltage. The A/D conversion system can report a change in, or a failure of, the A/D converter or its reference voltage, and can operate or prevent operation of protection elements.

The present disclosure provides systems and methods for identifying failures in an analog to digital (A/D) converter. An intelligent electronic device (IED) may monitor a digital output of one or more A/D converters. The IED may determine a slope value limit associated with the A/D converter. The IED may determine an output slope value of the digital output based on a difference of a converter output value measured at a first time and a converter output value measured at a later time. If the determined output slope value exceeds the slope value limit, the IED may identify a failure of the A/D converter. An IED may determine that concurrent failures in multiple, parallel A/D converters are indicative of a problem upstream from the A/D converters.

A circuit portion is provided which is arranged to be operable in a test mode. The circuit portion includes a Successive Approximation Register Analog to Digital Converter, SAR ADC, and an input for a reference signal. The SAR ADC is arranged to generate a feedback signal having a duty cycle representing a time taken for the SAR ADC to complete an analogue to digital conversion. The SAR ADC can carry out a comparison of a duty cycle of the reference signal with the duty cycle of the feedback signal, and can generate an output signal comprising a digital representation of the comparison of the reference duty cycle and the feedback duty cycle.