A composite analog-to-digital converter (ADC) has a low resolution ADC configured to receive and digitize analog data, the low resolution ADC having a low resolution and a high operating speed, one or more high resolution ADCs configured to receive and digitize the analog data, the one or more high resolution ADCs having a resolution higher than the low resolution ADC, and an operating speed lower than the high operating speed of the low resolution ADC, a sample clock generator to provide a sample clock signal to the low resolution ADC and to a clock divider, a mixer to receive the analog data and connected to the one or more high resolution ADCs, a local oscillator connected to the mixer to allow the one or more high resolution ADCs to be tuned to sample a portion of a spectrum of the first ADC. A test and measurement instrument contains a composite ADC. A method of operating a composite analog-to-digital converter (ADC), includes receiving an analog signal at a low resolution ADC that operates at a high speed, receiving the analog signal at one or more high resolution ADCs that operate at a resolution higher than the low resolution ADC and at a lower speed than the operating speed of the low resolution ADC, tuning the high resolution ADC to phase align and time align a signal path for the one or more high resolution ADCs to the signal path for the low resolution ADC, producing a spectrum from the low resolution ADC, and producing a portion of the spectrum from the one or more high resolution ADCs.

An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. A first capacitor is coupled between the first and second transistors and a second capacitor is coupled between the third and fourth transistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.

A test and measurement instrument includes a coefficient storage facility coupled to a programmable filter. The coefficient storage facility is configured to store at least two pre-determined filter coefficient sets, and configured to pass a selected one of the at least two pre-determined filter coefficient sets to the filter based on a measurement derived using a compensation oscillator. The measurement may include clock delay and clock skew. In some examples the test and measurement instrument may additionally adjust clock delay and/or clock skew in addition to selecting appropriate filter coefficients.

A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M<K<L. The upsampling stage supplies analog output signal images in a plurality of Nyquist zones. In one aspect, the D/A stage supplies N deinterleaved analog values having a combined bandwidth of M Hz, where N(P/2)=M.

A comparator offset calibration system having a comparator offset evaluator and a switched-capacitor network is disclosed, which is in an analog and digital dual domain structure. The comparator offset evaluator receives digital data from an analog-to-digital conversion module, evaluates an offset of a comparator of the analog-to-digital conversion module based on the received digital data, and outputs an evaluated result. The switched-capacitor network processes the evaluated result to generate a control signal. The analog-to-digital conversion module adjusts the offset of the comparator according to the control signal.

Apparatus and associated methods relate to modulating polarity on sample outputs from a time-interleaved analog-to-digital converter (TIADC) as an input to a time skew extractor in a clock skew calibration control loop. In an illustrative example, a multiplier-mixer may impart a polarity change to every other data sample transmitted between the TIADC and the time skew extractor. In some examples, a multiplexer may select between the polarity modulated samples and non-polarity modulated samples before the multiplier-mixer. Selection between the polarity modulated samples and the non-polarity modulated samples may be based on, for example, determination of specific frequency bands of an analog input signal. Various embodiments may improve convergence of clock skew calibration control loops for analog input signals sampled with a TIADC near a Nyquist frequency.

An analog signal generating source comprising two or more digital-to-analog converters (DAC) combined to generate one or more frequency components. The analog signal source comprises a first path for generating substantially low frequency signals, the first path comprising a first one of the DACs; and a second path for generating substantially high frequency signals, the second path comprising a second one of the DACs. The analog signal source also comprises a data processor for processing an input signal and providing the processed input signal to the first and second paths; a combining circuit configured to combine outputs of the first and second paths into the source signal; a feedback portion configured to sense the source signal; and a servo loop configured to use the sensed source signal to adjust as need to maintain the source signal to substantially agree with the input signal.

A successive approximation type AD converter includes an in-phase voltage detection and supply circuit that supplies an in-phase voltage obtained by impedance voltage division of a first input analog signal and a second input analog signal to a first capacitance DA converter and a second capacitance DA converter. The first capacitance DA converter samples the first input analog signal with reference to the in-phase voltage, and the second capacitance DA converter samples the second input analog signal with reference to the in-phase voltage. After the sampling period ends, a comparator compares the output of the first capacitance DA converter and the output of the second capacitance DA converter, output voltages of the first capacitance DA converter and the second capacitance DA converter are changed by the control signal of a successive approximation logic unit on the basis of a comparison result, and comparison processing is repeated.

A photonically-sampled electronically-quantized analog-to-digital converter generates an optical signal comprising a series of optical pulses. The optical signal is split into a first and a second optical path. The split optical signal is detected in the first path and then the detected optical signal is converted to a reference digital signal. The split optical signal in the second path is modulated with an input RF signal and a plurality of demultiplexed RF-modulated optically-sampled signals is generated from the modulated optical signal. The plurality of demultiplexed RF-modulated optically-sampled signals is then pulse broadened, detected, and converted to a plurality of sampled-RF digital signals. The reference digital signal and the plurality of sampled-RF digital signals are digital signal processed to generate a digital representation of the input RF signal.

In general, the subject matter described in this disclosure can be embodied in an electronic instrument for signal acquisition. The instrument includes a user-selectable button to activate a switch and change a first digitizer from connecting to a first input to connecting to a second input, resulting in an input signal being provided to both the first digitizer and a second digitizer. The instrument includes a combiner to combine an output of the first digitizer and an output of the second digitizer, when the input signal is provided to both the first digitizer and the second digitizer, to generate an output signal that has been digitized using the first digitizer and the second digitizer, the output signal having a bandwidth that exceeds the first bandwidth of the first digitizer and that exceeds the second bandwidth of the second digitizer.