The present invention relates to an incremental analog to digital converter incorporating noise shaping and residual error quantization. In one embodiment, a circuit includes an incremental analog to digital converter, comprising a loop filter that filters an analog input signal in response to receiving a reset signal, resulting in a filtered analog input signal, and a successive approximation register (SAR) quantizer, coupled with the filtered analog input signal, that converts the filtered analog input signal to an intermediate digitized output of a first resolution based on a reference voltage, wherein the SAR quantizer comprises a feedback loop that shapes quantization noise generated by the SAR quantizer as a result of converting the filtered analog input signal; and a digital filter, coupled with the intermediate digitized output, that generates a digitized output signal of a second resolution, greater than the first resolution, by digitally filtering the intermediate digitized output.

An analog-to-digital conversion device is disclosed that independently executes each of events instructed by a host device. Each of analog-to-digital converters include an execution control unit, an event management unit that notifies of a synchronization instruction when a synchronous conversion event set up with a synchronous conversion operation is instructed as the event, and an operation control unit. When a particular one of the analog-to-digital converters receives the synchronization instruction and the execution control unit of the particular analog-to-digital converter is confirmed ready for the analog-to-digital conversion, the operation control unit in the particular analog-to-digital converter notifies the particular analog-to-digital converter is ready for the analog-to-digital conversion to the analog-to-digital converter other than the particular analog-to-digital converter, and instructs the execution control unit to execute the synchronous conversion event after a confirmation that all of the analog-to-digital converters are ready for the analog-to-digital conversion.

Methods and systems for analog-to-digital conversion using two side branches that may be operated with overlapped timing such that a sampling phase may be overlapped with a previous conversion phase. Some embodiments provide a method of successive approximation A/D converting, comprising sampling a first signal onto a first capacitor that is configured to selectively couple to an analog input of a comparator, sampling a second signal onto capacitors that are coupled to a second analog input of the comparator and configured for charge redistribution successive approximation A/D conversion; carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the capacitors; and while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a third capacitor that is configured to selectively couple to the analog input of a comparator.

A signal control device includes a charge/discharge circuit, a sampling capacitor, and an AC conversion circuit. The charge/discharge circuit is capable of charging or discharging the sampling capacitor. The AC conversion circuit performs an AD conversion by converting an analog voltage value charged in the sampling capacitor into an AD conversion value that is a digital value. After a charge operation or a discharge operation to the sampling capacitor with the charge/discharge circuit, the AD conversion circuit performs the AD conversion, and a malfunction of the charge/discharge circuit is determined based on a diagnosis result of the AD conversion value.

An image sensor may contain an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to a column line which is used to read out imaging signals from the pixels. The column line may be coupled to an analog-to-digital converter for converting analog imaging signals from the pixels to digital signals. The analog-to-digital converter may be implemented as a charge sharing successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include a comparator coupled to a feedback digital-to-analog converter (DAC). The comparator may have a non-zero comparator offset. The feedback DAC may include capacitors that are scaled using a sub-radix-2 sizing scheme to help improve tolerance to the comparator offset while enabling resolutions of up to 10-bits or more.

Methods and systems for analog-to-digital conversion using two side branches that may be operated with overlapped timing such that a sampling phase may be overlapped with a previous conversion phase. Some embodiments provide a method of successive approximation A/D converting, comprising sampling a first signal onto a first capacitor that is configured to selectively couple to an analog input of a comparator, sampling a second signal onto capacitors that are coupled to a second analog input of the comparator and configured for charge redistribution successive approximation A/D conversion; carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the capacitors; and while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a third capacitor that is configured to selectively couple to the analog input of a comparator.

A sample and hold system, for capturing and reading at least one input signal. The system comprises a readout device, a controller, an array of segments comprising a plurality of unit cells and a dummy unit cell, and segment switches between the segments and the readout device. The controller is adapted for controlling the system such that: during an acquisition phase a trace of samples is taken from the input signal and held in the unit cells; during a readout phase the samples in the unit cells or in the dummy unit cells of a segment are read out by readout device; after opening or closing the segment switches the dummy unit cell, is the first cell which is read out by the readout device.

A broadband linear processing system includes a pre-processing module and a set of M linear processors coupled to the pre-processing module, M being an integer greater than 1. The pre-processing module includes a wavefront multiplexer having M input ports and M output ports. The wavefront multiplexer receives M input signals at the M input ports, performs a wavefront multiplexing transform on the M input signals and outputs M narrowband signal streams at the M output ports. The wavefront multiplexing transform has an inverse. Each of the M linear processors receives and processes a corresponding one of the M narrowband signal streams, and outputs a corresponding one of M processed narrowband signal streams.

An Analog-to-Digital-Conversion control system includes a first sample and hold circuit configured to provide a first sampled output to be converted by an Analog-to-Digital-Converter, which comprises a first sampling control circuit configured to receive a first trigger information to trigger sampling of a first analog input and to receive a first collision detection information from the Analog-to-Digital-Converter to detect a collision, a first sample and hold stage coupled to the first sampling control circuit and configured to sample the first analog input, only if no collision has been detected by the first sampling control circuit, wherein the first sampling control circuit is further configured to check predefined first sampling criteria and to output a first conversion request to the Analog-to-Digital-Converter, only if the predefined first sampling criteria are fulfilled.

Methods and systems are disclosed for using a single receiving device, such as a single VSA, to capture and digitize multiple time-domain acquisitions of a repeating signal at different center frequencies, to create a single time-domain waveform having a bandwidth greater than the real-time instantaneous bandwidth of the receiving device. Specifically, one or more signal processing paths may process the multiple digitized acquisitions of the repeating signal, either sequentially or in parallel, such that the processed acquisitions may be aggregated into a representation of one or more repetitions of the repeating signal.