A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.

Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting. In one aspect, first electrical charges are stored at a first capacitor according to the input voltage to obtain a second voltage. In one aspect, the second voltage is amplified according to the first electrical charges stored by the first capacitor to obtain a third voltage. In one aspect, second electrical charges are stored at the second capacitor according to the third voltage. In one aspect, the third voltage is amplified according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.

A signal processing assembly for a detector includes a signal amplifier, a control unit, and an offset control module. The signal amplifier is configured to receive an input signal from the detector assembly and to provide an output signal. The control unit is configured to compare a first data point from the output signal with a signal range, and to generate an input bias control signal based upon the comparison. The offset control module is coupled with the control unit and configured to receive the input bias control signal. The offset control module includes a power supply operatively coupled with an input of the signal amplifier, and the offset control module is configured to generate and apply an adaptive input offset signal at the input of the signal amplifier based upon the input bias control signal.

In a digital signal processing circuit that performs AD conversion using a comparison device and a counter, the speed of the AD conversion is increased. An attenuation unit, in a case where the level of an input signal exceeds a predetermined threshold value, attenuates the input signal and outputs it as an output signal. The comparison device compares the output signal with a predetermined reference signal that changes with lapse of time, and outputs the comparison result. The counter counts a count value until the comparison result is inverted and outputs a digital signal indicating the count value. The digital signal processing unit performs multiplication processing on the digital signal.

An electrical meter (M) installed at a facility (F) supplied electrical power by a utility's (U) electrical distribution system (EDS) utilizes a two-way automatic communications system (TWACS) for receiving messages from the utility sent over the electrical distribution system using the TWACS. An improvement to the meter comprises reconfiguring existing components installed in the meter to function as an analog-to-digital (ADC) converter so to facilitate processing of powerline waveforms (WF) propagated through the electrical distribution system by application of a signal based detection algorithm. This improves detection of signal elements comprising a message sent via the TWACS and by other means and incorporated in the electrical waveforms thereby reducing occurrence of a false synchronization with the message elements so a content of a message is readily ascertained by the meter.

Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting. In one aspect, first electrical charges are stored at a first capacitor according to the input voltage to obtain a second voltage. In one aspect, the second voltage is amplified according to the first electrical charges stored by the first capacitor to obtain a third voltage. In one aspect, second electrical charges are stored at the second capacitor according to the third voltage. In one aspect, the third voltage is amplified according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.

An integrated circuit (IC) includes an analog to digital converter (ADC) circuit having an ADC input and an ADC output. The ADC circuit is configured to receive an input signal at the ADC input and generate a digital output signal at the ADC output based on the input signal. An ADC circuit path is coupled between the ADC input and the ADC output. The ADC circuit comprises a plurality of capacitors coupled between reference voltage sources and the ADC circuit path. The ADC has a reconfigurable resolution and a reconfigurable sampling rate. The ADC circuit is configured to scale the reference voltage sources and/or the plurality of capacitors based on the reconfigurable resolution.

A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The front-end circuit may generate an equalized signal using multiple signals that encode a serial data stream of multiple data symbols. Based on a baud rate of the serial data stream, a determined number of the multiple analog-to-digital converter circuits sample, using a recovered clock signal, the equalized signal at the respective times to generate corresponding samples. The recovery circuit generates, using the samples, the recovered clock signal and recovered data symbols.

A real-time digital sparkle filter for processing high-speed analog to digital converter (ADC) data is disclosed. The real-time digital sparkle filter for processing a continuous stream of digital data, comprising a high-speed data interface, a digital sparkle filter, and a buffer sequencer. The high-speed data interface receives sample data from an analog to digital converter (ADC). The digital sparkle filter operates continuously on the sample data without losing any samples. The digital sparkle filter comprises one or more logic implemented using field-programmable gate arrays (FPGAs) configured to continuously process the data without degrading the signal content. The buffer sequencer comprises an input buffer and an output buffer. The input buffer receives the digital data stream data using a first in first out buffer mechanism. The output buffer receives the processed output of the sparkle filter, thereby eliminating the sparkle noise without degrading data content.

One example discloses a reconfigurable analog to digital converter (ADC) device, including: an analog front end (AFE) configured to receive a set of analog input signals and generate a corresponding set of digital output signals; wherein the AFE includes a set of reconfigurable ADC conversion circuits; and a sequencer coupled to the AFE and configured to control the set of reconfigurable ADC conversion circuits with a first AFE channel configuration at a first time and a second AFE channel configuration at a second time.