Embodiments may relate to a circuit for use in an analog-to-digital converter (ADC) circuit. The circuit may include a first residue amplifier stage and a second residue amplifier stage. The circuit may further include a synthesized delay stage with a digital-to-analog converter (DAC) electrically positioned between a signal input and the input of the second residue amplifier stage. The circuit may further include a resistor electrically positioned between the signal input and the input of the second residue amplifier stage. Other embodiments may be described or claimed.

A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device has a first input terminal and a second input terminal for receiving a received signal and an adjustable reference voltage respectively, and for generating an output signal at an output port. The first digital-slope quantizer is coupled to the output port and the second input terminal for generating a first set of digital signals to monotonically adjust the adjustable reference voltage at the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer is coupled to the output port and the second input terminal for generating a second set of digital signals to monotonically adjust the adjustable reference voltage at the second input terminal during a second phase after the first phase according to a second quantization unit.

An A/D conversion device, which operates in one mode including at least one of a mode, a cyclic mode, and a hybrid mode, includes: a first block that processes an analog input signal by a first amplifier; a second block including a second amplifier; a quantization unit that quantizes one of outputs of the first and second blocks; and a control circuit that switches the mode to perform a control corresponding to the mode.

An image sensor may include an array of image sensor pixels that are read out using analog-to-digital converters (ADCs). The ADC may be shot-noise-matched to reduce the number of decision cycles required. A ramp with limited resolution spanning only a small portion of the full scale voltage range may be used. For small analog input voltages, this limited ramp range is sufficient. For large analog input voltages, less resolution is needed due to the increasing shot noise in the photo signal. The larger input voltages may be successively divided by a selected attenuation factor until the analog input signal is within the range of the reduced ramp. The ADC keeps track of the number of divisions being performed to determine an exponent value for a floating-point output value and then convert the residual signal with the smaller ramp to determine a mantissa value for the floating-point output value.

Embodiments may relate to a circuit for use in an analog-to-digital converter (ADC) circuit. The circuit may include a first residue amplifier stage and a second residue amplifier stage. The circuit may further include a synthesized delay stage with a digital-to-analog converter (DAC) electrically positioned between a signal input and the input of the second residue amplifier stage. The circuit may further include a resistor electrically positioned between the signal input and the input of the second residue amplifier stage. Other embodiments may be described or claimed.

The present technology relates to a conversion apparatus, an imaging apparatus, an electronic apparatus, and a conversion method that are capable of reducing the scale of a circuit. The conversion apparatus includes: a comparison unit that compares an input voltage of an input signal and a ramp voltage of a ramp signal that varies with time; and a storage unit that holds a code value when a comparison result from the comparison unit is inverted, the holding of the code value by the storage unit being repeated a plurality of times, to generate a digital signal having a predetermined bit number. The predetermined bit number is divided into high-order bits and low-order bits, the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other, to generate the digital signal having the predetermined bit number. The present technology can be applied to a portion of an image sensor, in which AD conversion is performed.

A digital correlated double sampling (CDS) circuit includes a first latch circuit, a first converting circuit, a second converting circuit, a second latch circuit, and a calculating circuit. The first latch circuit latches an input phase shift code based on a first control signal to store first and second phase shift codes. The first converting circuit converts the first and second phase shift codes into first and second Gray codes. The second converting circuit converts the first Gray code and the second Gray code into a first binary code and a second binary code. The second latch circuit latches an output of the second converting circuit based on a second control signal to store the first binary code. The calculating circuit operates on the first binary code and the second binary code to generate a third binary code, and outputs the third binary code.

An analog-to-digital conversion devices and methods that approach a linear relationship between resolution and oversampling rate. The process involves modulating an input analog signals with an essentially chaotic encoding signal that is deterministic, aperiodic in that it lacks spectral tones above a threshold, and bounded. The resulting encoded signal is quantized into a bit stream and decoded by applying to that bit stream a non-linear estimation related to said chaotic signal to thereby produce an output representing said input analog signal in digital form.

The present invention relates to a converting device for converting an analog voltage into a digital number and to an imaging system comprising the same. The invention further relates to a method for converting an analog voltage into a digital number. According to the invention, one or more charge pumping steps are performed that change a voltage over a capacitive element that has been set in dependence of the voltage to be converted. During each charge pumping step, one or more substantially identical charge packets may be transferred to of from the capacitive element. The magnitude of the charge packets belonging to different charge pumping steps may be different allowing multi-slope operation. The digital number representing the analog voltage is calculated based on the net charge that has been injected into or removed from the main capacitive element as a result of having performed the one or more charge pumping steps.

Provided is an ADC in which a plurality of pixel signals input through a vertical signal line of a solid-state image pickup apparatus are held in advance using some capacitors among a plurality of capacitors within the ADC. A potential of a node is generated by the respective pixel signals held in the capacitors. Thereafter, the potential of the node is changed by changing the voltages of counter electrodes of the capacitors, and the digital values of the pixel signals are generated by comparing the potential of the node with a predetermined potential.