A SAR ADC includes a first capacitor array, a first comparator, a second capacitor array, a second comparator, an arbiter and a control circuit. The first capacitor array is arranged for receiving an input signal to generate a first signal. The first comparator is arranged for comparing the first signal with a first reference signal to generate a first comparison result. The second capacitor array is arranged for receiving the input signal to generate a second signal. The second comparator is arranged for comparing the second signal with a second reference signal to generate a second comparison result. The arbiter is arranged for generating an arbitration result according to the first comparison result and the second comparison result. The control circuit is arranged for generating an output signal according to the first comparison result, the second comparison result and the arbitration result.

The present invention relates to a converting device for converting an analog voltage into a digital number and to an imaging system comprising the same. The invention further relates to a method for converting an analog voltage into a digital number.

According to the invention, one or more charge pumping steps are performed that change a voltage over a capacitive element that has been set in dependence of the voltage to be converted. During each charge pumping step, one or more substantially identical charge packets may be transferred to of from the capacitive element. The magnitude of the charge packets belonging to different charge pumping steps may be different allowing multi-slope operation.

The digital number representing the analog voltage is calculated based on the net charge that has been injected into or removed from the main capacitive element as a result of having performed the one or more charge pumping steps.

An image detector includes an array of detector unit cells including a plurality of unit cells and a plurality of single slope analog to digital converters (SSADCs). Each of the plurality of SSADCs is coupled to an output of a different one of the unit cells. Each each of the plurality of SSADCs includes: a comparator having a positive input and a negative input and a comparator output, the comparator being contained in a first layer; and a counter coupled to the comparator output and contained in a second layer. The counter is electrically coupled to the comparator with a through a silicon via.

An analog-to-digital converter includes a cycle processing unit and a control unit. The cycle processing unit converts an analog input signal into a digital signal having a plurality of bits by performing a plurality of cycle processing on the analog input signal to acquire values of each bit in order from a higher-order bit to a lower-order bit. The control unit controls the cycle processing unit such that a period of the cycle processing is shortened according to a cycled number of the cycle processing.

An A/D converter includes an A/D conversion circuit for converting an analog output signal into a digital signal, and a control circuit for controlling the A/D conversion circuit. The control circuit acquires a digital signal of a first bit indicating which level regions the voltage level of the analog output signal corresponds to in accordance with a first conversion operation by the A/D conversion circuit, sets a reference voltage corresponding to the level region based on the first bit, amplifies the difference voltage between the analog output signal and the reference voltage to correspond to the A/D conversion input range of the A/D conversion circuit, outputs an amplified analog signal, acquires a digital signal of a second bit indicating the voltage level of the amplified analog signal in accordance with a second conversion operation by the A/D conversion circuit, and synthesizes the first bit and the second bit.

The present technology relates to a conversion apparatus, an imaging apparatus, an electronic apparatus, and a conversion method that are capable of reducing the scale of a circuit. The conversion apparatus includes: a comparison unit that compares an input voltage of an input signal and a ramp voltage of a ramp signal that varies with time; and a storage unit that holds a code value when a comparison result from the comparison unit is inverted, the holding of the code value by the storage unit being repeated a plurality of times, to generate a digital signal having a predetermined bit number. The predetermined bit number is divided into high-order bits and low-order bits, the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other, to generate the digital signal having the predetermined bit number. The present technology can be applied to a portion of an image sensor, in which AD conversion is performed.

An image sensor pixel may include a photodiode, a floating diffusion, and a transfer gate. Column readout circuitry coupled to the image sensor pixel via a column line. The column readout circuitry may include sample and hold circuitry, comparison circuitry, residual measurement and summation circuitry, counter circuitry, analog-to-digital conversion circuitry, and digital summation circuitry. Column readout circuitry is configured to perform readout operations on a pixel image signal generated for a single frame in one or more portions, thereby extending the dynamic range of the imaging system without modifying pixel structure to generate high-dynamic range images within the single frame.

The present technology relates to a conversion apparatus, an imaging apparatus, an electronic apparatus, and a conversion method that are capable of reducing the scale of a circuit.

The conversion apparatus includes: a comparison unit that compares an input voltage of an input signal and a ramp voltage of a ramp signal that varies with time; and a storage unit that holds a code value when a comparison result from the comparison unit is inverted, the holding of the code value by the storage unit being repeated a plurality of times, to generate a digital signal having a predetermined bit number. The predetermined bit number is divided into high-order bits and low-order bits, the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other, to generate the digital signal having the predetermined bit number. The present technology can be applied to a portion of an image sensor, in which AD conversion is performed.

An image detector includes an array of detector unit cells including a plurality of unit cells and a plurality of single slope analog to digital converters (SSADCs). Each of the plurality of SSADCs is coupled to an output of a different one of the unit cells. Each each of the plurality of SSADCs includes: a comparator having a positive input and a negative input and a comparator output, the comparator being contained in a first layer; and a counter coupled to the comparator output and contained in a second layer. The counter is electrically coupled to the comparator with a through a silicon via.

Multiple-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuits are disclosed. In one aspect, a multiple-bit parallel SAR ADC circuit includes a number of SAR controller circuits, each of which includes SAR register circuits. Each SAR register circuit receives and stores a corresponding digital bit that is based on a comparison of an analog input signal and a corresponding digital-to-analog converter (DAC) analog signal. Each SAR register circuit also provides a corresponding digital signal based on the digital bit. A DAC circuit receives a reference voltage, and uses the reference voltage and a subset of digital signals generated by SAR controller circuits to generate multiple DAC analog signals. A compare circuit generates the digital bit corresponding to each SAR controller circuit, wherein a number of the digital bits are generated in parallel. Each digital bit collectively forms a digital representation of the analog input signal.