The present invention discloses an analog to digital conversion (ADC) apparatus having quick conversion mechanism. Each of ADC circuits receives a previous higher-bit conversion result to perform prediction to generate a current higher-bit conversion result, performs conversion on an input analog signal according to a sampling clock that has a frequency at least twice of the frequency of the input analog signal based on a successive-approximation mechanism to generate a current lower-bit conversion result, and combines the current higher-bits and current lower-bit conversion results to generate a current conversion result and output a remained signal amount as a residue. A noise-shaping circuit performs calculation based on the residue to generate a noise-shaping reference signal. Each of the ADC circuits combines the current conversion result and the noise-shaping reference signal to generate an output digital signal.

Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, a system comprises a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W− values, and wherein one of the columns in the second array is a dummy column; wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)−(W−).

An apparatus and a method. The apparatus includes a delay processor, a coarse converter and node selector connected to the delay processor and configured to select a first voltage V.sub.1 and a second voltage V.sub.2 of opposite polarities of adjacent stages of the delay processor, a fine converter connected to the coarse converter and node selector and configured to determine a zero-crossing time associated with the first voltage V.sub.1 and the second voltage V.sub.2; and an encoder connected to the coarse converter and the fine converter and configured to receive and encode the first voltage V.sub.1, the second voltage V.sub.2 and the zero-crossing time, wherein V.sub.1 is a first negative voltage before the zero-crossing time, and V.sub.2 is a first positive voltage after the zero-crossing time.

A hybrid analog-to-digital converter (ADC) includes a plurality of analog-to-digital conversion circuits and a combining circuit. The analog-to-digital conversion circuits generate a plurality of partial digital outputs for a same analog input, respectively, wherein the analog-to-digital conversion circuits include a digital slope ADC used to perform signal quantization in a time domain. The combining circuit combines the partial digital outputs generated from the analog-to-digital conversion circuits to generate a final digital output of the analog input.

A pipelined ADC system comprising: a first ADC stage comprising a trainable neural network layer and configured to receive an analog input signal, and convert it into a first n-bit digital output representing said analog input signal; a DAC circuit comprising a trainable neural network layer and configured to receive said first n-bit digital output, and convert it into an analog output signal representing said first n-bit digital output; and a second ADC stage comprising a trainable neural network layer and configured to receive a residue analog input signal of said analog input signal, and convert it into a second n-bit digital output representing said residue analog input signal; wherein said first and second n-bit digital outputs are combined to generate a combined digital output representing said analog input signal.

A sum-of-products calculation apparatus is provided. The sum-of-products calculation apparatus includes an analog-to-digital (A-to-D) conversion circuit having an encoder circuit and a plurality of inverters. Threshold voltages of the inverters are set according to classification threshold values of an activation function. The inverters generate a plurality of bit signals in response to an analog sum-of-products signal. The encoder circuit encodes the bit signals to generate a digital signal.

In one form, a signal chain circuit includes a signal chain processing circuit between an input for receiving a differential input signal having a first common-mode voltage, and an output for providing a differential output signal having a second, different common-mode voltage. It includes an amplifier with a differential output stage coupled to a differential input stage and having positive and negative output terminals forming its output, and positive and negative feedback terminals. The differential output stage provides a first voltage drop between the positive output terminal and the positive feedback terminal, and a second voltage drop between the negative output terminal and the negative feedback terminal. The common-mode feedback circuit regulates a common-mode voltage between the positive and negative feedback terminals to the second common-mode voltage. In another form, an analog-to-digital converter includes a range extending logic circuit to extend the range of a ring oscillator based analog-to-digital converter.

A readout circuit includes a ramp generator for generating a plurality of first short ramps having a first level in a reset conversion phase and a plurality of second short ramps having a second level greater than the first level and a full-scale ramp having a third level greater than the second level in a signal conversion phase, a comparator for comparing a first analog signal with each one of the first short ramps to obtain a plurality of first comparison results in the reset conversion phase, and comparing a second analog signal with each one of the second short ramps and the full-scale ramp in the signal conversion phase to generate a plurality of second comparison results and a third comparison result, and a controller configured to determine an output signal value of the second analog signal according to the plurality of second comparison results and the third result.

An analog-to-digital converter includes: a voltage-current converter receiving an analog input voltage, generating a first digital signal from the analog input voltage, and outputting a residual current remaining after the first digital signal; a current-time converter converting the residual current into a current time in a time domain; and a time-digital converter receiving the residual time, and generating a second digital signal from the residual time, wherein the first digital signal and the second digital signal are sequences of digital codes representing respective signal levels of the analog input voltage.

The disclosure belongs to the field of integrated circuits, and is used for reducing an area overhead and a power consumption of a pipelined analog-to-digital converter. Each stage of the pipelined analog-to-digital converter according to the disclosure comprises an analogue-to-digital converter, a digital-to-analog converter, a subtractor and an amplifier. According to the disclosure, an amplification time of the pipelined ADC is used for extra quantization, and a number of bits of each ADC is reduced on the premise of not increasing a number of stages of the pipelined ADC, so that a scale of each circuit is greatly reduced, and the power consumption and the area overhead are reduced.