A method is provided for measuring time varying particle fluxes with improved temporal resolution and signal to noise ratio. The particles can be photons, neutrons, electrons or electrically charged particles. The method includes a set of electronic and/or optical components and a set of algorithms that implement N-fold temporal multiplexing of the input flux. The system can be used to measure other types of flux by using a transducer to convert the flux into a compatible form. The system can include a transducer such as a scintillator that operates to convert particle flux incident into a photon flux proportional to the amplitude of particle flux. The invention can be used with multiplexing methods known to those skilled in the art, for example Hadamard and Fourier methods.

In one aspect, a transfer function (TF) estimation circuit configured to generate an estimate of a TF undergone by signals between an input of a digital-to-analog converter (DAC) of a feedforward path of a continuous-time (CT) stage of an analog-to-digital converter (ADC) and an output of a backend ADC of the ADC is disclosed. The TF estimation circuit includes one or more circuits configured to generate a first cross-correlation output by cross-correlating digital versions of signals based on a test signal provided to the CT stage and an output signal of the backend ADC, generate a second cross-correlation output by cross-correlating digital versions of signals based on the test signal and an output signal of a quantizer of the feedforward path of the CT stage, and generate the estimate of the TF based on the first and second cross-correlation outputs.

An analog-to-digital converter includes a first converter stage, a second converter stage coupled to the first converter stage to quantize a residue signal of the first converter stage, and an inter-stage converter disposed between the first and second converter stages. The inter-stage converter is configured to convert between a first domain and a second domain. The inter-stage converter is configured to process the residue signal of the first converter stage such that a range of the residue signal matches a full scale of the second converter stage.

An analog-to-digital converter (ADC) circuit comprises one or more most-significant-bit (MSB) capacitors having first ends connected to a voltage comparator and one or more least-significant-bit (LSB) capacitors having first ends connected to the comparator. The circuit further comprises a first switching circuit for each MSB capacitor, configured to selectively connect the second end of the respective MSB capacitor to (a) an input voltage, for sampling, (b) a ground reference, during portions of a conversion phase, and (c) a first conversion reference voltage, for other portions of the conversion phase. The circuit still further comprises a second switch circuit, for each LSB capacitor, configured to selectively connect the second end of the respective LSB capacitor between (d) the ground reference, during portions of the conversion phase, and (e) a second conversion reference voltage, for other portions of the conversion phase, the second conversion reference voltage differing from the first.

A sample and hold (S/H) circuit includes an analog-to-digital converter (ADC), a register and a digital-to-analog converter (DAC). The ADC receives an input signal and converts the input signal into a digital code. The register, coupled to the ADC, stores the digital code. The DAC, coupled to the register, converts the digital code into an output signal.

An analog-to-digital converter has a first digital signal generator that generates a first digital signal based on whether or not a sampling signal of an input signal is equal to or lower than a signal corresponding to a second reference signal higher than a first reference signal, a first slope generator to generate a first slope signal that changes with time from the sampled and held signal equal to or lower than the first reference signal, a second slope generator to generate a second slope signal that changes with time from the sampled and held signal to a signal level equal to or lower than the second reference signal, and a second digital signal generator that generates a second digital signal based on a time at which the first slope signal matches the first reference signal or a time at which the second slope signal matches the second reference signal.

An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current mode DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.

An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.

An analog-to-digital converter includes a first converter stage, a second converter stage coupled to the first converter stage to quantize a residue signal of the first converter stage, and an inter-stage converter disposed between the first and second converter stages. The inter-stage converter is configured to convert between a first domain and a second domain. The inter-stage converter is configured to process the residue signal of the first converter stage such that a range of the residue signal matches a full scale of the second converter stage.

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.