A solid-state imaging device includes a first converter which converts an analog signal representing a pixel value to an upper bit of a digital signal, and a second converter which converts the analog signal to a lower bit of the digital signal. The second converter includes a first latch circuit which latches, as phase information, a plurality of clock signals having different phases upon conversion to the upper bit in the first converter, a conversion circuit which generates the lower bit of the digital signal by converting the phase information to a binary value, and an adder, and a second latch circuit which latches an addition result of the adder. The adder adds the binary value converted by the conversion circuit and a value latched by the second latch circuit.

The present invention provides a semiconductor device having an integration type A/D converter capable of speeding up. The semiconductor device includes a Johnson counter 18 for transmitting a lower bit counter signal JC<3:0>, a lower bit latch circuit 11 for outputting a lower bit latch result signal by a lower bit counter signal JC<3:0> and a lower bit latch signal 14, a determination circuit 12 for outputting an upper bit latch signal 15 by a lower bit latch signal 14, a binary gray converter circuit 20 for transmitting an upper bit counter signal GR<n:3>, and an upper bit latch circuit 13 for outputting an upper bit latch result signal by an upper bit counter signal GR<n:3> and an upper bit latch signal 15.

A pipelined ADC system comprising: a first ADC stage comprising a trainable neural network layer and configured to receive an analog input signal, and convert it into a first n-bit digital output representing said analog input signal; a DAC circuit comprising a trainable neural network layer and configured to receive said first n-bit digital output, and convert it into an analog output signal representing said first n-bit digital output; and a second ADC stage comprising a trainable neural network layer and configured to receive a residue analog input signal of said analog input signal, and convert it into a second n-bit digital output representing said residue analog input signal; wherein said first and second n-bit digital outputs are combined to generate a combined digital output representing said analog input signal.

An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.

Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W− values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)−(W−). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W− values.

A sub-ranging analog-to-digital converter (ADC) includes a coarse ADC and a fine ADC that receives a set of coarse signals from the coarse ADC. The fine ADC includes multiple digital-to-analog converters (DACs) and multiple converters such that a number of converters is less than a number of DACs. The DACs and the converters function in a partial time-interleaved manner where each DAC receives an analog input signal in different non-overlapping durations of a clock signal and generates a corresponding analog output signal. At least one of the converters is coupled with at least two DACs, and each converter is configured to receive the corresponding analog output signals and perform conversion operation to generate digital signals in non-overlapping durations of the clock signal, respectively. The durations for performing conversion operation of at least two of the converters overlap partially.

An analog-to-digital converter (“ADC”) has an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal. A second ADC stage is coupled to the first ADC stage and is configured to convert the analog residue signal to a second digital value. At least one of the first ADC stage and the second ADC stage includes a first sub-stage configured to convert an analog signal to a first number of bits of a digital value representing the analog signal, and a second sub-stage configured to convert the analog signal to a second number of bits of the digital value, where the second number of bits is greater than the first number of bits. A controller is coupled to the first and second ADC stages and configured to combine the first digital value and the second digital value into a digital output signal representing the analog input voltage signal.

An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.