An ADC circuit that can resolve the most significant bits (MSBs) using a first circuit during a first stage of a multi-stage conversion and resolve the least significant bits (LSBs) using a second circuit during a second stage of the multi-stage conversion. This can be used, for example, in massively parallel applications where the reference level generation can be shared between thousands of converters.

An analog-to-digital converter (ADC) device includes an ADC circuitry and a digital slope ADC circuitry. The ADC circuitry is configured to generate first bits and a first voltage according to an input signal. The digital slope ADC circuitry is configured to generate a second voltage at a node according to the first voltage and to gradually adjust the second voltage to generate second bits. After the second bits are generated, the digital slope ADC circuitry is further configured to perform a noise shaping function according to a first residual signal of the node.

An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.

The present application discloses an N-bit hybrid-structure analog-to-digital converter and an integrated circuit chip including the same, including a pre-stage sampling capacitor array, a post-stage capacitor array and a comparator set and the pre-stage sampling capacitor array including a number of 2.sup.N1 sets of first capacitor array units arranged in parallel, the first capacitor array unit including two sets of parallel capacitor strings, input terminals of parallel capacitor strings respectively being connected to and switchable between differential analog signals and first preset reference signals, output terminals of the parallel capacitor strings respectively being connected to input terminals of the comparator set, input terminals of the post-stage capacitor array respectively being connected to and switchable between output terminals of the comparator set and differential analog signals, output terminals of the post-stage capacitor array being configured as an output terminal of the analog-to-digital converter.

A multiple-input analog-to-digital converter device includes analog-to-digital converter circuits arranged between input nodes and output nodes. The analog-to-digital converter circuits operate over respective conversion times to provide simultaneous conversion of the analog input signals into respective conversion time signals. A time-to-digital converter circuit includes timer circuitry common to the plurality of analog-to-digital converter circuits. The timer circuitry cooperates with the analog-to-digital converter circuits to convert the conversion time signals into digital output signals at the output nodes.

A multi-stage analog-to-digital converter (ADC) suitable for low power applications, such as glucose monitoring, may be required to digitize a slow-moving signal. As such, a multi-stage ADC must be versatile. Accordingly, the multi-stage ADC can be configured to operate at different bandwidths and resolutions through the use of ADC stages that can be enabled or disabled in an exchange between resolution and speed. Each ADC stage digitizes an input signal (e.g., a voltage or a current) using an analog comparison to access a lookup table for a digital signal that represents the input signal at a particular accuracy. Unlike other multi-stage approaches, the digitization is asynchronous (i.e., requires no clock) and can provide simplicity, speed, and low-power operation to the multi-stage ADC.

A multi-stage analog-to-digital converter (ADC) suitable for low power applications, such as glucose monitoring, may be required to digitize a slow-moving signal. As such, a multi-stage ADC must be versatile. Accordingly, the multi-stage ADC can be configured to operate at different bandwidths and resolutions through the use of ADC stages that can be enabled or disabled in an exchange between resolution and speed. Each ADC stage digitizes an input signal (e.g., a voltage or a current) using an analog comparison to access a lookup table for a digital signal that represents the input signal at a particular accuracy. Unlike other multi-stage approaches, the digitization is asynchronous (i.e., requires no clock) and can provide simplicity, speed, and low-power operation to the multi-stage ADC.

A conventional analog-to-digital conversion circuit has a problem that conversion errors cannot be suppressed. According to one embodiment, the analog-to-digital conversion circuit includes a first digital-to-analog conversion circuit 30 of a capacitance distribution type, a second digital-to-analog conversion circuit 31 of a capacitance distribution type, and a comparison circuit 32 for comparing output voltages of the two digital-to-analog conversion circuits, and before performing a successive comparison operation for successively changing a reference voltage applied to the first digital-to-analog conversion circuit, generates an intermediate digital value having a digital value corresponding to a voltage value of an analog input signal, determines a reference voltage to be applied to the second digital-to-analog conversion circuit 31 in accordance with the intermediate digital value, and thereafter performs a successive comparison operation using the first digital-to-analog conversion circuit 30 in a state in which the state of the second digital-to-analog conversion circuit 31 is held.

A clock-less delay comparator coupled to a first input signal and a second input signal, the clock-less delay comparator comprising: a first transistor having a control terminal coupled to the second input signal, a first current terminal coupled to a first voltage supply, and a second current terminal; a second transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a third transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fourth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fifth transistor having a control terminal coupled to the second input signal, a first current terminal, and a second current terminal coupled to the control terminal of the third transistor; a sixth transistor having a control terminal coupled to the first input signal, a first current terminal, and a second current terminal coupled to the control terminal of the second transistor and the second current terminal of the third transistor; a seventh transistor having a control terminal coupled to the control terminal of the second transistor, a first current terminal coupled to a second voltage supply, and a second current terminal coupled to the first current terminal of the fifth transistor; an eighth transistor having a control terminal coupled to the control terminal of the third transistor, a first current terminal coupled to the second voltage supply, and a second current terminal coupled to the first current terminal of the sixth transistor; a ninth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the second current terminal of the first transistor, and a second current terminal coupled to the second current terminal of the second transistor and the second current terminal of the fifth transistor; and a tenth transistor having a control terminal coupled to the second input signal, a first current terminal coupled to the second terminal of the fourth transistor, and a second current terminal coupled to the second current terminal of the third transistor.

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.