The present invention provides a comparator circuit applicable to a high-speed pipeline ADC. The comparator circuit includes a switch capacitor circuit, a pre-amplification circuit, and a latch circuit. The pre-amplification circuit includes a pre-amplifier, a resistance-adjustable device, two switches. The latch circuit includes a differential static latch, a first capacitor, a second capacitor, and a third switch. The transmission rates of a sampling phase and a setup phase can be increased.

An analog-to-digital converter includes a first converter stage, a second converter stage coupled to the first converter stage to quantize a residue signal of the first converter stage, and an inter-stage converter disposed between the first and second converter stages. The inter-stage converter is configured to convert between a first domain and a second domain. The inter-stage converter is configured to process the residue signal of the first converter stage such that a range of the residue signal matches a full scale of the second converter stage.

An analog-to-digital converter configured to convert an analog signal into a digital signal includes a first converter configured to receive an input signal of an analog type, compare the input signal with a plurality of reference signals, select one of the plurality of reference signals based on the comparison, and output an upper bit that is a portion of the digital signal based on the selected reference signal, a second converter configured to perform an oversampling operation n times based on a residue signal indicating a difference between an upper analog signal corresponding to the upper bit value and the input signal and output an intermediate bit value of the digital signal corresponding to the first to n-th oversampling signals generated respectively during the oversampling operations performed n times, and a third converter configured to output a lower bit value of the digital signal corresponding to the n-th oversampling signal.

A multiple-input analog-to-digital converter device includes analog-to-digital converter circuits arranged between input nodes and output nodes. The analog-to-digital converter circuits operate over respective conversion times to provide simultaneous conversion of the analog input signals into respective conversion time signals. A time-to-digital converter circuit includes timer circuitry common to the plurality of analog-to-digital converter circuits. The timer circuitry cooperates with the analog-to-digital converter circuits to convert the conversion time signals into digital output signals at the output nodes.

The present disclosure relates to a compensation circuit for compensating for an offset voltage that is present in an output signal output by a force sensor. The compensation circuit comprises: voltage divider circuitry, the voltage divider circuitry configured to receive a bias voltage that is also supplied to the force sensor and to output a control voltage derived from the bias voltage, wherein a component mismatch ratio of the voltage divider circuitry is adjustable to correspond to a component mismatch ratio of the force sensor; current generator circuitry configured to receive the control voltage and to generate a compensating current based on the received control voltage; and amplifier circuitry configured to receive the differential signal output by the force sensor and the compensating current and to output a compensated differential output signal in which the offset voltage is at least partially cancelled.

The present disclosure provides digital to analog conversion circuitry comprising: a set of input nodes for receiving a digital input code; an output node for outputting an analog output signal representative of the input code; and a plurality of selectable conversion elements, wherein a parameter of each of the plurality of selectable conversion elements is configured such that a transfer function between the input code and the output analog signal is non-monotonic.

The present disclosure provides digital to analog conversion circuitry comprising: a set of input nodes for receiving a digital input code; an output node for outputting an analog output signal representative of the input code; and a plurality of selectable conversion elements, wherein a parameter of each of the plurality of selectable conversion elements is configured such that a transfer function between the input code and the output analog signal is non-monotonic.

Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W− values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)−(W−). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W− values.

Apparatuses and techniques are described for providing a positive voltage source and a negative voltage source in a circuit. The positive voltage source and the negative voltage source have a common ground node. The positive voltage source can be provided using a current mirror in which a current in a first path is copied to provide a current in a second path. The currents of the first and second paths are sunk at the common ground node. The negative voltage source can be provided using a current mirror in which a current in a third path is copied to provide a current in a fourth path, where the current of the fourth path is sourced at the common ground node.

A pipelined ADC that does not wait for the residue of a signal to settle to be delivered to the next stage of the pipeline, and thus passes signals to subsequent stages at faster than conventional speeds is described. A pipelined ADC is used that processes signals representing the boundaries of the search space. Thus, each stage does not necessarily receive the signal as pre-processed by the prior stage, but rather the search space boundaries as pre-processed by the prior stage. Reducing the “search space” of the ADC is equivalent to creating the residues in each step of a pipeline as in the prior art. An ADC operating in this fashion operates without error even if the residual search space boundary outputs from one state are presented to the next stage before the outputs have settled, and can run faster for a given power and bandwidth.