The present technology relates to a signal processing device, an imaging element, and an electronic apparatus configured so that a cost increase can be suppressed.

A signal processing device of the present technology includes: a comparison unit configured to compare a signal level of an analog signal with a signal level of a reference signal; a selection unit configured to select, from a plurality of reference signals, the reference signal to be supplied to the comparison unit; and a switching unit capable of switching a signal line connected to an input terminal of the comparison unit such that a signal line via which the reference signal selected by the selection unit is transmitted is connected to the input terminal of the comparison unit, wherein the comparison unit includes a floating node as the input terminal, the selection unit includes a signal line in which a parasitic capacitance is caused between the signal line and the floating node as the input terminal of the comparison unit, and the signal line of the selection unit is configured to transmit an identical level of signal in multiple comparison processes performed by the comparison unit. The present technology is applicable to, e.g., an imaging element and an electronic apparatus.

When a level of a signal output from a pixel is higher than a comparison level, the signal output from the pixel is converted into a digital signal during a first period by using a first reference signal. If the level of the signal output from the pixel is lower than the comparison level, the signal output from the pixel is converted into a digital signal during a second period that is longer than the first period by using a second reference signal.

The present technology relates to a signal processing device, an imaging element, and an electronic apparatus configured so that a cost increase can be suppressed. A signal processing device of the present technology includes: a comparison unit configured to compare a signal level of an analog signal with a signal level of a reference signal; a selection unit configured to select, from a plurality of reference signals, the reference signal to be supplied to the comparison unit; and a switching unit capable of switching a signal line connected to an input terminal of the comparison unit such that a signal line via which the reference signal selected by the selection unit is transmitted is connected to the input terminal of the comparison unit, wherein the comparison unit includes a floating node as the input terminal, the selection unit includes a signal line in which a parasitic capacitance is caused between the signal line and the floating node as the input terminal of the comparison unit, and the signal line of the selection unit is configured to transmit an identical level of signal in multiple comparison processes performed by the comparison unit. The present technology is applicable to, e.g., an imaging element and an electronic apparatus.

A method and a circuit are arranged for adapting a first reference value for generating a first bit stream from an input signal by a first amplitude adapting unit. The input signal comprises a first and a second signal. The first signal and the second signal form a baseband sum signal. A first non-linear component demodulates the input signal and outputs a demodulated input signal. The amplitude adapting unit outputs the first bit stream from the demodulated input signal on the basis of a first reference value. A reference-value adapting unit comprises a detection unit which detects the first and the second signal. Upon discontinuation of the first and second signals, an adjusting unit adjusts the first reference value to a basic reference value.

An electronic device which may include an analog-to-digital converter circuit that converts a level of an input signal to digital input values in response to a clock signal, an oscillator that generates the clock signal, a first equalization circuit that generates digital output signals by equalizing the digital input values, a first phase detector circuit that detects phases of the digital output signals and generates digital phase values, a loop filter that generates a first digital output value based on the digital phase values, a second equalization circuit that generates digital intermediate values by equalizing the digital input values, and a second phase detector circuit that detects phases of the digital intermediate values and to generate a second digital output value. The oscillator may adjust a frequency of the clock signal based on the first digital output value and the second digital output value.

A semiconductor device configured to perform an A/D conversion of a wide range of signals is provided. A semiconductor device includes: an input voltage detection unit configured to detect an analog input voltage; a reference voltage setting unit configured to set a reference voltage based on the detected input voltage; an amplifier configured to amplify a difference between the input voltage and the reference voltage; an ADC configured to perform an A/D conversion of an amplified signal; and an arithmetic processing unit configured to calculate a digital voltage corresponding to the input voltage based on a result of the A/D conversion and the reference voltage.

When a level of a signal output from a pixel is higher than a comparison level, the signal output from the pixel is converted into a digital signal during a first period by using a first reference signal. If the level of the signal output from the pixel is lower than the comparison level, the signal output from the pixel is converted into a digital signal during a second period that is longer than the first period by using a second reference signal.

When a level of a signal output from a pixel is higher than a comparison level, the signal output from the pixel is converted into a digital signal during a first period by using a first reference signal. If the level of the signal output from the pixel is lower than the comparison level, the signal output from the pixel is converted into a digital signal during a second period that is longer than the first period by using a second reference signal.

A semiconductor device configured to perform an A/D conversion of a wide range of signals is provided. A semiconductor device includes: an input voltage detection unit configured to detect an analog input voltage; a reference voltage setting unit configured to set a reference voltage based on the detected input voltage; an amplifier configured to amplify a difference between the input voltage and the reference voltage; an ADC configured to perform an A/D conversion of an amplified signal; and an arithmetic processing unit configured to calculate a digital voltage corresponding to the input voltage based on a result of the A/D conversion and the reference voltage.

An image capturing device includes: an image capturing section having a plurality of pixels disposed in a matrix and configured to output a pixel signal via a first signal line connected to pixels arranged in a first direction among the plurality of pixels; a plurality of calculators including: a comparator configured to compare a magnitude of a first analog signal with a threshold value to generate a digital value according to a comparison result; an amplification section configured to amplify the first analog signal by multiplying the first analog signal by an amplification degree (1<<2) and output a second analog signal by executing computation according to the digital value; and a switching section configured to output one of the pixel signal and a estimation signal as the first analog signal when a most significant bit of a first digital value sequence is computed.