Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

A device for receiving RF signal is provided. The device includes a receiving component configured to receive a radio frequency (RF) signal and a sampling component configured to sample the RF signal. The sampling component may include a plurality of filters, a demultiplexer, a clock synthesizer, an analog-to-digital converter (ADC), and a digital signal processing device. The sampling component may obtain an intermediate frequency (IF) signal based on the plurality of filters, the demultiplexer, the clock synthesizer, the ADC, and the digital signal processing device.

The value range for which an error in a digital signal can be corrected is expanded. A control unit generates characteristic information indicating the relationship between an input and an output of an A/D converter and sets a value range. The control unit, in a case in which a value indicated by a first digital signal obtained by the A/D converter converting a first analog voltage signal is within the value range, A/D converts the first analog voltage signal and generates corrected digital information on the basis of the first digital signal and characteristic information, and in a case in which a value indicated by the first digital signal is not within the value range, A/D converts the first analog voltage signal and generates corrected digital information on the basis of a second digital signal obtained by the A/D converter converting the second analog voltage signal and characteristic information.

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

A receive path arrangement of a radar sensor of FMCW type comprising a first and second receive path configured to receive reflected radar signals for detection and ranging of objects in a space around the radar sensor; the first receive path configured to provide reflected radar signals between a first and second beat frequency to a first analogue to digital converter for subsequent digital signal processing and wherein; the second receive path includes a second-receive-path filter configured to provide filtered signals by attenuation of the reflected radar signals having frequencies below an intermediate beat frequency, the intermediate beat frequency between the first and second beat frequencies, the second receive path further including a second-receive-path amplifier arrangement configured to provide amplified signals by amplification of the filtered signals and provide the amplified signals to a second analogue to digital converter for subsequent digital signal processing.

Embodiments of methods and systems for gain control in a communications device are described. In an embodiment, a method for gain control in a communications device involves detecting a change in an amplification gain that is applied to an analog signal in the communications device and compensating for the change in the amplification gain by manipulating an amplitude of a digital signal that is converted from the analog signal. Other embodiments are also described.

There is described a switchable microphone device which may be switched between a digital output mode and an analog output mode. There is further described a system for use of such a device, which allows for the switching between analog and digital computing modes.

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

A measurement system includes a source unit to provide a source signal to a sample and a voltage source and/or a current source and a memory. The system also includes a measurement unit configured to acquire from the sample an measurement signal that may be responsive to the source signal and a voltage measuring unit, a current measuring unit, and/or a capacitance measuring unit, and a memory. The system also includes a control unit including a digital signal processing unit; a source converter; a measurement converter. The system further includes a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, the measurement converter, the source unit, and the measurement unit; a calibration unit for calibrating aspects of the system including the control unit; and a reference voltage supply configured to supply a common reference voltage for the control unit.

The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.