A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2.sup.(K+1) steps, each of which has a value equal to an integer multiplying 2.sup.(−K) of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2.sup.(K+1) number of N-bit digital signals based on the at least 2.sup.(K+1) steps of the digitally controlled offset voltage, summing the at least the 2.sup.(K+1) number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.

An image sensor may contain an array of imaging pixels. Each pixel column outputs signals that are read out using a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include at least first and second input sampling capacitors, a comparator, a capacitive digital-to-analog converter (CDAC), and associated control circuitry. If desired, the SAR ADC may include a bank of more than two input sampling capacitors alternating between sampling and conversion. The first capacitor may be used to sample an input signal while conversion for the second capacitor is taking place. Prior to conversion, an input voltage of the comparator and an output voltage of the CDAC may be initialized. During conversion of the signal on the first capacitor, the first capacitor is embedded within the SAR ADC feedback loop to prevent charge sharing between the input sampling capacitor and the CDAC, thereby mitigating potential capacitor mismatch issues.

An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N−K)th capacitor, and a constant binary weight from the (N−K)th capacitor to a (N−K−2+2.sup.(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2.sup.(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.

An analog-to-digital conversion devices and methods that approach a linear relationship between resolution and oversampling rate. The process involves modulating an input analog signals with an essentially chaotic encoding signal that is deterministic, aperiodic in that it lacks spectral tones above a threshold, and bounded. The resulting encoded signal is quantized into a bit stream and decoded by applying to that bit stream a non-linear estimation related to said chaotic signal to thereby produce an output representing said input analog signal in digital form.

A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2.sup.(K+1) steps, each of which has a value equal to an integer multiplying 2.sup.(−K) of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2.sup.(K+1) number of N-bit digital signals based on the at least 2.sup.(K+1) steps of the digitally controlled offset voltage, summing the at least the 2.sup.(K+1) number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.

The A/D converter includes a D/A conversion circuit configured to perform a D/A conversion on a DAC input digital value to output a DAC output signal, a difference output circuit for outputting difference signals based on a difference between the input signal and the DAC output signal, an A/D conversion circuit for performing an A/D conversion on the difference signals to output an ADC output digital value, and a control circuit for outputting the DAC input digital value based on the ADC output digital value. The control circuit outputs a first DAC input digital value and a second DAC input digital value different from the first DAC input digital value, and obtains ADC result data based on a first ADC output digital value obtained in accordance with the first DAC input digital value, a second ADC output digital value obtained in accordance with the second DAC input digital value, and the DAC input digital value.

According to an aspect, there is provided an apparatus comprising a combiner for combining a received analog signal with an analog dithering signal to produce a combined analog signal, a one-bit analog-to-digital converter for converting the combined analog signal to a combined digital signal, means for performing joint downsampling and feature extraction for the combined digital signal, means for implementing a trained machine-learning algorithm for calculating one or more input parameters for waveform generation at least based on one or more features extracted from the combined digital signal and a parametric waveform generator for generating the analog dithering signal based on the one or more input parameters.

An image forming includes a dither processing unit that applies a dither matrix to an image; an exposure unit that exposes a photosensitive drum to form an electrostatic latent image based on the image to which the dither matrix has been applied; a development unit that develops, using a developing material on a developing roller, the formed electrostatic latent image; and a control unit that, based on a print setting change instruction by a user, increases a circumferential speed of the developing roller relative to the circumferential speed of the photosensitive drum and decreases a screen ruling of the dither matrix to be applied by the dither processing unit.

A circuit device includes a clock generation circuit, a signal generation circuit, a phase comparison circuit, and a processing circuit. The signal generation circuit generates a first signal making the transition at a transition timing of a first clock signal, a fine-judging signal making the transition at a transition timing of a second clock signal, a first coarse-judging signal making the transition at a transition timing of the second clock signal anterior to the fine-judging signal, and a second coarse-judging signal making the transition at a transition timing of the second clock signal posterior to the fine-judging signal. The phase comparison circuit performs the phase comparison between the second signal making the transition based on the first signal and each of the fine-judging signal, the first coarse-judging signal, and the second coarse-judging signal. The processing circuit sets the transition timing of the first signal and the transition timing of the fine-judging signal based on the phase comparison result, and converts a time difference between the first signal and the second signal into a digital value based on the setting result.

According to an aspect, there is provided an apparatus comprising a combiner for combining a received analog signal with an analog dithering signal to produce a combined analog signal, a one-bit analog-to-digital converter for converting the combined analog signal to a combined digital signal, means for performing joint downsampling and feature extraction for the combined digital signal, means for implementing a trained machine-learning algorithm for calculating one or more input parameters for waveform generation at least based on one or more features extracted from the combined digital signal and a parametric waveform generator for generating the analog dithering signal based on the one or more input parameters.