A digitally-controlled oscillator (DCO) circuit includes a digital-to-analog converter (DAC) to generate a first current based on most significant bits of a multi-bit code received from a time-to-digital converter (TDC) of a digital phase-locked loop (PLL). The DCO circuit further includes a sigma-delta modulator (SDM) to modulate least significant bits of the multi-bit code into a set of digital bits based on a first frequency of a feedback clock of the DPLL. The set of digital bits is to cause the DAC to generate a second current. The DCO circuit further includes a ring oscillator coupled to the DAC, the ring oscillator to generate an alternating-current (AC) output signal having a second frequency corresponding to a combination of the first current and the second current.

A range profile digitization circuit for converting a repeating analog input signal into a time series of digital amplitude values, the converter comprising: a signal quantizer arranged to receive the analog input signal and a threshold input and arranged to output a binary value quantized output signal based on a comparison of the input signal with the threshold signal; a plurality of samplers each arranged to sample and hold its input signal upon receipt of a trigger signal; and for each sampler: a plurality of decoders and a demultiplexer arranged to receive an output from the sampler and pass it to a selected one of said decoders based on a selector input. With a plurality of decoders associated with each of the samplers, each sampler can be re-used during the building up of the range profile.

A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC, and includes a notch filter. The interference detection path is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter. The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter to attenuate the interference signal.

A mixed-signal controller for controlling a multiphase average-current-mode voltage regulator having an output connected to a load, which comprises a digital voltage-sampling ADC for converting the output voltage signal from analog to digital representation; a digital current-sampling ADC, for converting the inductor current from analog to digital representation; a digital compensator for generating a current reference signal, based on a digital voltage error signal and for generating a duty-ratio command signal, based on a digital current error signal; a multiphase Digital Pulse Width Modulator (DPWM), for generating a pulse-width-modulated signal (per-phase), to thereby control the per-phase currents and output voltage supplied to the load; an analog front-end, in which single-ended signals are used for steady-state control via ADC measurement and the single-ended output voltage is used for transient detection and output voltage extremum detection during transient; a Transient Suppression Unit (TSU), for generating gating signals being fed to the gates of the converter's transistors during a transient event; a Phase Count Optimizer (PCO) unit generating an enable/disable control signal to each phase PWM output tri-state buffer; an Active Voltage Positioning (AVP) unit for generating the voltage loop compensator voltage reference signal.

A digital lock-in controller for Resonant-type converters with one or more sub-circuits having resonant tanks and one or more flying capacitors connected across the resonant tanks, which comprises an auto-tuner that receives as input Zero-Current Detect (ZCD) signals and implements a tuning algorithm by performing arithmetic operations that ensure Zero-Current Switching (ZCS) operation for all resonant tanks in the converter; a digital hybrid High-Resolution (HR) sequencer that receives as input the switching times commands and generates a pulse-width-modulated signal that is fed into the gates of the converter's switching transistors; a sampling block with time resolution of a single delay-element, for accurately reading of the ZCD sensor's outputs; a governor module for performing all synchronization actions and dictating the operation mode of the controller, based on auxiliary configurations.

An analog-to-digital converter (ADC) having an input operable to receive an input voltage, V.sub.IN, and an output operable to output a digital code representative of V.sub.IN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.

A system for converting a voltage into output codes includes logic gates for processing delay signals based on earlier and later arriving signals generated by preamplifiers, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits of the codes, and an auxiliary delay comparator for generating an auxiliary digital signal for use in generating the output codes. A system may include logic gates for generating delay signals based on earlier and later arriving signals, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits, and a multiplexer system for transmitting a selected one of the residue signals.

A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.

An analog-to-digital converter (ADC) having an input operable to receive an input voltage, V.sub.IN, and an output operable to output a digital code representative of V.sub.IN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.

A multiple-input analog-to-digital converter device includes analog-to-digital converter circuits arranged between input nodes and output nodes. The analog-to-digital converter circuits operate over respective conversion times to provide simultaneous conversion of the analog input signals into respective conversion time signals. A time-to-digital converter circuit includes timer circuitry common to the plurality of analog-to-digital converter circuits. The timer circuitry cooperates with the analog-to-digital converter circuits to convert the conversion time signals into digital output signals at the output nodes.