A capacitance-to-digital-converter includes a first delay block configured to output a first signal after a first delay based on a voltage at a capacitive sensor, the capacitive sensor configured to be iteratively discharged; a second delay block configured to output a second signal after a second delay; and a capacitance determination unit configured to determine a value indicative of a capacitance sensed by the capacitive sensor. This determination is based on: a number of clock periods during which the first delay is less than a third delay; a first time difference between receipt of the first signal and the second signal during a last clock period during which the first delay is less than the third delay; and a second time difference between receipt of the first signal and receipt of the second signal during a first clock period during which the first delay is greater than the third delay.

Digital calibration systems and related methods are disclosed for multi-stage analog-to-digital converters (ADCs). For one embodiment, a multi-stage ADC includes an initial ADC, an additional ADC, and calibration logic. The initial ADC generates an output signal and N-bit digital values that are based upon an input signal. The additional ADC receives the output signal from the initial ADC and generates M-bit digital values that are based upon the output signal. The calibration logic receives the N-bit digital values and the M-bit digital values and generates correction values. The correction values are based upon differences between maximum values and minimum values for M-bit digital values associated with different regions determined by the N-bit digital values. Digital conversion outputs for the multi-stage ADC are provided as combinations of the N-bit digital values and the M-bit digital values corrected with the correction values.

An A-D conversion circuit configured to convert an analog input signal into numerical data using a pulse delay circuit includes pulse position digitizing units, a clock generation circuit, and a processing unit. The clock generation circuit includes inverters each including one or more n-channel transistors and one or more p-channel transistors. The inverters differ from each other in a number ratio of the number of n-channel transistors connected in a common-gate parallel-connected manner and the number of p-channel transistors connected in a common-gate parallel-connected manner.

A digital controller for controlling an average-current-mode voltage regulator with an output connected to a load. The controller comprises a digital voltage-sampling window Analog-to-Digital Converter (ADC), based on Delay-Lines (DLs) and configured to obtain a sample of a voltage error signal being the difference between the reference voltage and the output voltage, and to convert the voltage error signal from analog to digital representation; a digital current-sampling window ADC, based on DLs and configured to obtain a sample of the output current and to convert the current output from analog to digital representation; a digital compensator for voltage regulation, receiving as input the digital voltage error signal, configured to generate a current reference signal based thereupon; a digital compensator for current regulation, receiving as input the current error signal and the current reference signal, configured to generate a duty-ratio command signal based thereupon; and a digital hybrid High Resolution (HR) Digital Pulse Width Modulator (HR-DPWM) receiving as input the duty-ratio command signal and generating a pulse-width-modulated signal that is fed to the gates of the converter's transistors, to thereby control the current and voltage supplied to the load.

A range profile digitization circuit for converting a repeating analog input signal into a time series of digital amplitude values, the converter comprising: a signal quantizer arranged to receive the analog input signal and a threshold input and arranged to output a binary value quantized output signal based on a comparison of the input signal with the threshold signal; a plurality of samplers each arranged to sample and hold its input signal upon receipt of a trigger signal; and for each sampler: a plurality of decoders and a demultiplexer arranged to receive an output from the sampler and pass it to a selected one of said decoders based on a selector input. With a plurality of decoders associated with each of the samplers, each sampler can be re-used during the building up of the range profile.

A time-to-voltage converter includes a switched-capacitor circuit configured to charge an output node to a reset voltage level in a first interval of a conversion period and configured to shift a voltage on the output node from the reset voltage level to a shifted reset voltage level in a second interval of the conversion period. The time-to-voltage converter includes a current source selectively coupled to the output node. The current source is configured to provide a constant current to the output node in a third interval of the conversion period. The shifted reset voltage level is outside a voltage range defined by a first power supply voltage level on a first voltage reference node and a second power supply voltage level on a second voltage reference node.

A transition-state output device includes: a ring oscillator circuit; a state machine changing in state according to a change in state of the ring oscillator circuit; a transition-state acquisition section acquiring and holding state information including a signal output from the ring oscillator circuit and a signal output from the state machine, synchronously with a reference signal; and an internal-state calculation section calculating an internal state corresponding to a number of changes in state of the ring oscillator circuit, based on the state information held by the transition-state acquisition section. A time until the internal state, after transitioning from a first internal state to a second internal state, transitions to the first internal state again is longer than a time interval of updating the state information held by the transition-state acquisition section.

A transition-state output device includes: a ring oscillator circuit; a state machine changing in state according to a change in state of the ring oscillator circuit; a transition-state acquisition section acquiring and holding state information including a signal output from the ring oscillator circuit and a signal output from the state machine, synchronously with a reference signal; and an internal-state calculation section calculating an internal state corresponding to a number of changes in state of the ring oscillator circuit, based on the state information held by the transition-state acquisition section. A time until the internal state, after transitioning from a first internal state to a second internal state, transitions to the first internal state again is longer than a time interval of updating the state information held by the transition-state acquisition section.

A mixed-signal controller for controlling a multiphase average-current-mode voltage regulator having an output connected to a load, which comprises a digital voltage-sampling ADC for converting the output voltage signal from analog to digital representation; a digital current-sampling ADC, for converting the inductor current from analog to digital representation; a digital compensator for generating a current reference signal, based on a digital voltage error signal and for generating a duty-ratio command signal, based on a digital current error signal; a multiphase Digital Pulse Width Modulator (DPWM), for generating a pulse-width-modulated signal (per-phase), to thereby control the per-phase currents and output voltage supplied to the load; an analog front-end, in which single-ended signals are used for steady-state control via ADC measurement and the single-ended output voltage is used for transient detection and output voltage extremum detection during transient; a Transient Suppression Unit (TSU), for generating gating signals being fed to the gates of the converter's transistors during a transient event; a Phase Count Optimizer (PCO) unit generating an enable/disable control signal to each phase PWM output tri-state buffer; an Active Voltage Positioning (AVP) unit for generating the voltage loop compensator voltage reference signal.

An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.