A signal processing circuit for a gyroscope apparatus is disclosed. The signal processing circuit includes a first electrode and a second electrode pairing with the first electrode. The signal processing circuit, being a negative feedback loop circuit, is configured to be connected with the first electrode and the second electrode and comprises a demodulator configured to convert a current from the first electrode into a voltage and demodulate the converted voltage to output a demodulated signal, an analog-to-digital converter configured to convert the demodulated signal from the demodulator into a digital signal, a proportional-integral-derivative controller that is connected to the analog-to-digital converter, a digital-to-analog converter configured to convert an output signal from the proportional-integral-derivative controller to an analog signal, and a modulator configured to be electrically connected with the second electrode and to be electrically connected with the digital-to-analog converter.

The present disclosure relates to circuitry comprising: digital circuitry configured to generate a digital output signal; and monitoring circuitry configured to monitor a supply voltage to the digital circuitry and to output a control signal for controlling operation of the digital circuitry, wherein the control signal is based on the supply voltage.

The present disclosure relates to circuitry comprising: pulse-width modulation (PWM) circuitry configured to generate a PWM output signal; and monitoring circuitry configured to monitor a supply voltage to the PWM circuitry and to output a control signal for controlling operation of the PWM circuitry, wherein the control signal is based on the supply voltage.

A circuit for decoding a pulse width modulated (PWM) signal generates an output signal switching between a first and second logic values as a function of a duty-cycle of the PWM signal. Current generating circuitry receives the PWM signal and injects a current to and sinks a current from an intermediate node as a function of the values of the PWM signal. A capacitor coupled to the intermediate node is alternatively charged and discharged by the injected and sunk currents, respectively, to generate a voltage. A comparator circuit coupled to the intermediate node compares the generated voltage to a comparison voltage and drives the logic values of the output signal as a function of the comparison.

Technologies are provided for time-to-digital conversion without reliance on a clocking signal. The technologies include a clockless TDC apparatus that can map continuous pulse-widths to binary bits represented via an iterative chaotic map (e.g., tent map, Bernoulli shift map, or similar). The clockless TDC apparatus can convert separated pulses to a single asynchronous digital pulse that turns on when a sensor detects a first pulse and turns off when the sensor detects a second pulse. The asynchronous digital pulse can be iteratively stretched and folded in time according to the chaotic map. The clockless TDC can generate a binary sequence that represents symbolic dynamics of the chaotic map. The process can be implemented by using an iterative time delay component until a precision of the binary output is either satisfied or overwhelmed by noise or other structural fluctuations of the TDC apparatus.

In an embodiment an isolated gate driver device includes a low-voltage section having a control input configured to receive a PWM control signal with a switching frequency from a control stage, a high-voltage section, galvanically isolated from the low-voltage section the high-voltage section including a driving output configured to provide a gate-driving signal as a function of the PWM control signal to a power stage having at least one switch, a feedback input configured to receive at least one feedback signal indicative of an operation of the power stag, and an ADC module configured to convert the feedback signal into a digital data stream and a conversion-control module coupled to the ADC module and configured to provide a conversion-trigger signal designed to determine a start of a conversion for acquiring a new sample of the feedback signal.

In an embodiment a method includes receiving, at an input of a low-voltage section of a gate driver, a PWM control signal with a switching frequency, providing, at an output of a high-voltage section of the gat driver, a gate-driving signal as a function of the PWM control signal to a power stage, wherein the high-voltage section is galvanically isolated from the low-voltage section, receiving, at a feedback input of the high-voltage section, at least one feedback signal indicative of an operation of the power stage, converting, at an ADC module of the high-voltage section, the feedback signal into a digital data stream, providing, to the ADC module, a conversion-trigger signal designed to determine a start of a conversion for acquiring a new sample of the feedback signal and sending, via an isolation communication channel between the low-voltage section and the high-voltage section, the digital data stream to the low-voltage section.

This application relates to time-encoding modulators (TEMs). A TEM receives an input signal (S.sub.IN) and outputs a time-encoded output signal (S.sub.OUT). A filter arrangement receives the input signal and also a feedback signal (S.sub.FB) from the TEM output, and generates a filtered signal (S.sub.FIL) based, at least in part, on the feedback signal. A comparator receives the filtered signal and outputs a time-encoded signal (S.sub.PWM) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp, capacitance and switch network. In the first mode the op-amp is enabled, and coupled with the capacitance to provide the active filter. In the second mode the op-amp is disabled and the capacitance is coupled to a signal path for the feedback signal to provide a passive filter.

The present disclosure relates to circuitry comprising: digital circuitry configured to generate a digital output signal; and monitoring circuitry configured to monitor a supply voltage to the digital circuitry and to output a control signal for controlling operation of the digital circuitry, wherein the control signal is based on the supply voltage.

A calibration circuit, including: a first analog-to-digital converter (ADC) configured to sample a nonlinear reference signal continuously at an equidistant sampling rate to generate a reference sampled signal; a trigger timer configured to generate trigger signals; a second ADC configured to sample a point of each of the nonlinear reference signal and repeated versions of the nonlinear reference signal in response to the respective trigger signals at equidistantly increasing delays, to generate a device-under-test (DUT) sampled voltage; and processing circuitry configured to estimate a differential nonlinearity (DNL) of the DUT sampled signal, estimate a DNL of the reference sampled signal, and compare the estimated DNL of the DUT sampled signal with the estimated DNL of the reference sampled signal, to generate a DNL performance indication signal of the second ADC.