A circuit is for sampling an analog input signal that receives and samples an analog input signal. Sampling circuitry is clocked at a sampling frequency and samples the analog input signal at a rate corresponding to the sampling frequency. The sampling circuitry includes at least one pulse density modulator that includes a comparator configured to be clocked at the sampling frequency, to provide bandpass sampling of the analog input signal at the sampling frequency, and to produce a corresponding pulsed output that is pulse density modulated based on the analog input signal.

A disclosed linearization circuit includes a reference component, a charging and discharging controller, and a comparator circuit. The reference component has a non-linear dependence on current or voltage. The charging and discharging controller is configured to control alternating charging and discharging of the reference component. A voltage associated with the reference component forms a reference signal. The charging and discharging are controlled such that the reference signal has a periodic time dependence. The reference signal and a measurement signal are received by the comparator circuit. The comparator circuit is configured to generate and output a square-wave signal based on a reference time point during a charge-discharge cycle, and based on a result of a comparison of the reference signal with the measurement signal, such that the square-wave signal represents a linearized output signal. This disclosure further relates to a corresponding method.

Various implementations of sorting networks are described that utilize time-encoded data signals having encoded values. In some examples, an electrical circuit device includes a sorting network configured to receive a plurality of time-encoded signals. Each time-encoded signal of the plurality of time-encoded signals encodes a data value based on a duty cycle of the respective time-encoded signal or based on a proportion of data bits in the respective time-encoded signal that are high relative to the total data bits in the respective time-encoded signal. The sorting network is also configured to sort the plurality of time-encoded signals based on the encoded data values of the plurality of time-encoded signals.

A field measuring device includes a sensor, a measuring transducer, and interface electronics. The interface electronics include a measuring and control device, and first and second terminals for connecting an external electrical device. A current controller and a current measuring device are connected in series in a terminal current path between the first and second terminals. The interface electronics has a voltage source that can be switched on in the terminal current path and disconnected from the terminal current path, so that the voltage source can drive a current in the terminal current path in the switched-on state and in the case of a connected external electrical device. The measuring and control device actuates and reads the current controller, the current measuring device, and the voltage source such that a current signal is output or input via the first and second terminals when an external device is connected.

A comparator circuit according to the present disclosure includes a first switch section that selectively takes in a signal voltage, a second switch section that selectively takes in a control waveform, a differential amplifier including a non-inverted input end connected to each of output ends of the first switch section and the second switch section, a capacity section including one end connected to an inverted input end of the differential amplifier and the other end supplied with a reference voltage, and a third switch section that selectively short-circuits the inverted input end and an output end of the differential amplifier.

This application relates to time-encoding modulators (TEMs). A TEM receives an input signal (S.sub.IN) and outputs a time-encoded output signal (S.sub.OUT). A filter arrangement receives the input signal and also a feedback signal (S.sub.FB) from the TEM output, and generates a filtered signal (S.sub.FIL) based, at least in part, on the feedback signal. A comparator receives the filtered signal and outputs a time-encoded signal (S.sub.PWM) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp, capacitance and switch network. In the first mode the op-amp is enabled, and coupled with the capacitance to provide the active filter. In the second mode the op-amp is disabled and the capacitance coupled to a signal path for the feedback signal to provide a passive filter.

A disclosed linearization circuit includes a reference component, a charging and discharging controller, and a comparator circuit. The reference component has a non-linear dependence on current or voltage. The charging and discharging controller is configured to control alternating charging and discharging of the reference component. A voltage associated with the reference component forms a reference signal. The charging and discharging are controlled such that the reference signal has a periodic time dependence. The reference signal and a measurement signal are received by the comparator circuit. The comparator circuit is configured to generate and output a square-wave signal based on a reference time point during a charge-discharge cycle, and based on a result of a comparison of the reference signal with the measurement signal, such that the square-wave signal represents a linearized output signal. This disclosure further relates to a corresponding method.

An ADC that includes a processing unit configured to receive from first sampling latches N first PWM pulse start counter values and N first PWM pulse end counter value, receive from second sampling latches, N second PWM pulse start counter values and N second PWM pulse end counter value; (c) select a counter that is coupled to a selected sampling latch; (d) calculate an estimated difference between first and second input analog signals based on at least readings of the selected latch. The readings of the selected counter include a first PWM pulse start counter value latched by the selected latch, a first PWM pulse end counter value latched by the selected latch, a second PWM pulse start counter value latched by the selected latch, and a second PWM pulse end counter value latched by the selected latch; and (e) output a digital output signal indicative of the estimated difference.

A system may include an output stage for driving a load at an output of the output stage, a pulse-width modulation mode path configured to pre-drive the output stage in a first mode of operation, a linear mode path configured to pre-drive the output stage in a second mode of operation and a loop filter coupled at its input to the output of the output stage and coupled at its output to both of the pulse-width modulation mode path and the linear mode path. The pulse-width modulation mode path and the linear mode path may be configured such that a first transfer function between the output of the loop filter and the output of the output stage is substantially equivalent to a second transfer function between the output of the loop filter and the output of the output stage

A system includes a central processing unit (CPU) core, and a pulse width modulator (PWM) controller configured to generate a PWM control signal having a PWM cycle. The system also includes an analog-to-digital converter (ADC), an accumulator, a sum register, and an oversampling register set. The oversampling register set is configurable by the CPU core to specify time points during each PWM cycle when the ADC is to convert an analog signal to a digital sample to produce a plurality of digital samples. The time spacing between consecutive digital samples varies among the specified time points. The accumulator accumulates digital samples from the ADC and stores an accumulated sum in the sum register. The CPU core reads the accumulated sum from the sum register, and can use the accumulated sum to calculate a metric (e.g., an average) of the digital samples.