The present invention relates to a converting device for converting an analog voltage into a digital number and to an imaging system comprising the same. The invention further relates to a method for converting an analog voltage into a digital number.

According to the invention, one or more charge pumping steps are performed that change a voltage over a capacitive element that has been set in dependence of the voltage to be converted. During each charge pumping step, one or more substantially identical charge packets may be transferred to of from the capacitive element. The magnitude of the charge packets belonging to different charge pumping steps may be different allowing multi-slope operation.

The digital number representing the analog voltage is calculated based on the net charge that has been injected into or removed from the main capacitive element as a result of having performed the one or more charge pumping steps.

An AD converter with self-calibration function that does not require an instrument for calibration, and includes: a reference voltage unit that generates a reference voltage; a summation and conversion unit that has two or more unit voltages serving as units of amount of change in a summed voltage, and during conversion, sums up any one unit voltage of the two or more unit voltages until the summed voltage exceeds the reference voltage, with an input voltage being an initial value of the summed voltage; and a control unit including a calibration control section that calibrates the two or more unit voltages and an offset voltage of a comparator at a time of calibration, and a conversion control section that determines a polarity of the offset voltage of the comparator and thereafter converts the input voltage to a digital value during conversion.

The present description concerns a method of controlling an analog-to-digital converter, wherein most significant bits are determined by successive approximations implementing a first digital-to-analog converter and a second digital-to-analog converter. Further, least significant bits are determined by a time-to-digital conversion by applying a first ramp to the output of the first converter with a third digital-to-analog converter and by applying a second ramp to the output of the second converter with a fourth digital-to-analog converter. The variation direction of the first and second ramps is determined by the comparison of the outputs of the first and second converters at the end of the successive approximations.

A receiver may include a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor. The receiver may also include a current buffer configured to drive the time-interleaved charge sampler.

An analog-to-digital converter (ADC) is disclosed. The ADC includes a successive approximation register and a voltage-to-time conversion element. The successive approximation register is configured to receive an input signal and to generate a first digital signal and a residue voltage. The voltage-to-time conversion element is configured to convert the residue voltage to a time domain representation. The voltage-to-time conversion element includes an amplifier having an input coupled to an output of the successive approximation register and configured to receive the residue voltage, and a zero crossing detector directly coupled to an output of the amplifier. A time-to-digital converter is coupled to an output of the zero crossing detector and is configured to generate a second digital signal.

A circuit is disclosed. The circuit includes a voltage-to-time conversion element configured to receive an input voltage at an input and to generate a time domain representation of the input voltage. The voltage-to-time conversion element includes an amplifier having an amplifier input coupled to the input, a zero crossing detector coupled to an output of the amplifier, and a current source selectively coupled to the amplifier input by way of a switching element.

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

A transition state acquisition device includes an oscillator that includes a tapped delay line and a combination circuit provided on a signal path from one end to the other end of the tapped delay line, and oscillates based on a first signal, and a latch that captures and holds an output signal of the tapped delay line in synchronization with a second signal. The oscillator starts a transition of a state of the tapped delay line based on the first signal. An interval between timings at which the latch captures the output signals of the tapped delay line is shorter than a time during which the state transition of the tapped delay line makes one round.

A transition state acquisition device includes an oscillator that includes a tapped delay line and a combination circuit provided on a signal path from one end to the other end of the tapped delay line, and oscillates based on a first signal, and a latch that captures and holds an output signal of the tapped delay line in synchronization with a second signal. The oscillator starts a transition of a state of the tapped delay line based on the first signal. An interval between timings at which the latch captures the output signals of the tapped delay line is shorter than a time during which the state transition of the tapped delay line makes one round.