An image sensing device including a pixel array including a plurality of pixels and an analog-to-digital converter (ADC) configured to convert an analog signal into a digital signal is provided. The ADC includes a first circuit configured to receive the analog signal from a selected pixel among the plurality of pixels and generate a first output signal and a second circuit including a select transistor configured to apply a voltage to a floating node electrically connected to the select transistor based on the first output signal. The second circuit further includes a capacitor connected in parallel between a gate and a drain of the select transistor and an output circuit connected to the floating node and configured to output the digital signal based on the applied voltage to the floating node.

A circuit includes a comparator configured to generate a first conversion gain output signal by comparing a first pixel signal corresponding to a first conversion gain with a first ramp signal, and generate a second conversion gain output signal by comparing a second pixel signal corresponding to a second conversion gain with a second ramp signal, and a counter configured to count pulses of the first conversion gain output signal, output a counting result as a first digital signal, and determine whether an output of a second digital signal corresponding to the second conversion gain is required, based on the first digital signal. The first conversion gain is higher than the second conversion gain, and based on determining that the output of the second digital signal is not required, the counter is further configured to control the comparator such that the second conversion gain output signal is not generated.

The present technology relates to a comparator that can easily modify operating point potential of the comparator, and an imaging device. A pixel signal output from a pixel, and, a reference signal with changeable voltage are input to a differential pair. A current mirror connected to the differential pair, and a voltage drop mechanism allowed to cause a predetermined voltage drop is connected between a transistor that configures the differential pair, and a transistor that configures the current mirror. A switch is connected in parallel to the voltage drop mechanism. The present technology can be applied, for example, to an image sensor that captures an image.

Adaptive-on-time techniques to improve the frequency variations inherent in constant-on-time COT converters are presented. A switching converter contains a power switch; a pulse generator adapted to generate a pulsed signal to switch the power switch on with a switching frequency; a ramp generator adapted to generate a ramp signal; and a controller adapted to detect a parameter of the ramp signal, compare the parameter with a reference value, and to generate a control signal based on the comparison to control the switching frequency. This allows controlling a switching frequency of the converter without increasing a noise level of the converter.

An image sensor includes: a pixel outputting a pixel signal; a ramp voltage generation circuit suitable for generating a ramp voltage that changes at a first slope in a first section and generating the ramp voltage that changes at a second slope having a greater absolute value than the first slope in a second section following the first section; an operation amplifier suitable for comparing the pixel signal with the ramp voltage during the first section and the second section; and a counter circuit suitable for generating a digital code corresponding to the pixel signal in response to an output of the operation amplifier.

An image sensor includes: a pixel outputting a pixel signal; a ramp voltage generation circuit suitable for generating a ramp voltage that changes at a first slope in a first section and generating the ramp voltage that changes at a second slope having a greater absolute value than the first slope in a second section following the first section; an operation amplifier suitable for comparing the pixel signal with the ramp voltage during the first section and the second section; and a counter circuit suitable for generating a digital code corresponding to the pixel signal in response to an output of the operation amplifier.

Apparatuses and methods for reducing vertical fixed pattern noise in imaging systems are disclosed herein. An example apparatus may include an analog dithering circuit coupled to randomly add an offset voltage to a first reference voltage in response to a random binary signal during an analog to digital conversion operation, and a ramp generator circuit coupled to receive the first reference voltage, and provide a second reference voltage in response, wherein the randomly added offset voltage to the first reference is also present in the second reference voltage.

A slope analog-to-digital converter, ADC, comprises: an input unit comprising a sampling capacitor, wherein the input unit is configured to during an initial period obtain a sampled value of an analog input signal and, during a conversion period, hold the sampled value across the sampling capacitor; and a comparator configured to determine a most significant bit of the analog input signal during the initial period; wherein the ADC during the conversion period is configured to receive a slope signal and to be adapted based on the determined most significant bit such that the comparator is further configured to adaptively compare the sampled value and the slope signal for converting the sampled value to a digital representation.

A semiconductor device with low power consumption can be provided. The semiconductor device includes a differential circuit and a latch circuit, the differential circuit includes a transistor including an oxide semiconductor in a channel formation region, and the latch circuit includes a transistor including a single semiconductor or a compound semiconductor in a channel formation region. The differential circuit and the latch circuit include an overlap region.

An analog-to-digital converter includes a comparator having paired differential input ends, and a first capacitor and a second capacitor each provided at respective differential input ends. The first capacitor includes a plurality of first sub-capacitors that are coupled side by side with one another, and the second capacitor includes a plurality of second sub-capacitors that are coupled side by side with one another. The plurality of first sub-capacitors and the plurality of second sub-capacitors are mixedly arranged in each column of a plurality of columns.