A PAM4 driver with at least 56 Gbps speed for driving a Mach-Zehnder modulator. The PAM4 driver is configured as 2-bit CMOS digital-to-analog convertor including a drive control module for receiving a pair of incoming differential digital data and generating a first processed reference signal and a second processed reference signal. The PAM4 driver further includes a mirrored buffer circuit to produce two sets of four voltage levels. Furthermore, the PAM4 driver includes a decoder module controlled by a switch bias control module configured to decode each of the two sets of four voltage levels for generating a first output signal and a complementary second out signal with 4 independently adjustable analog levels for driving the Mach-Zehnder modulator with close ended termination resistor.

A digital-to-analog converter (DAC) includes a plurality of segments, wherein the plurality of segments includes a first segment electronically coupled to each of the plurality of segments, wherein the first segment includes a predetermined number of most significant bits (MSB), a second segment electronically coupled to each of the plurality of segments, wherein the second segment includes a first predetermined number of least significant bits (LSB), and a third segment electronically coupled with each of the plurality of segments, wherein the third segment includes a second predetermined number of LSBs. Additionally, the DAC includes an all logic implementation.

A single chip dual-channel driver for two independent traveling wave modulators. The driver includes two differential pairs inputs per channel respectively configured to receive two digital differential pair signals. The driver further includes a two-bit DAC per channel coupled to the two differential pairs inputs to produce a single analog differential pair PAM signal at a differential pair output for driving a traveling wave modulator. Additionally, the driver includes a control block having internal voltage/current signal generators respective coupled to each input and the 2-bit DAC for providing a bias voltage, a tail current, a dither signal to assist modulation control per channel. Furthermore, the driver includes an internal I2C communication block coupled to a high-speed clock generator to generate control signals to the control block and coupled to host via an I2C digital communication interface.

Provided is a solid-state imaging device capable of increasing the speed of an A/D converter. The solid-state imaging device includes a successive approximation A/D converter that performs A/D conversion on an analog pixel signal. The successive approximation A/D converter includes a D/A converter, a comparator, and a successive approximation register. The D/A converter converts a digital reference signal to an analog reference signal. The successive approximation register operates based on the result of comparison by the comparator to generate the digital reference signal in such a manner that the analog reference signal approximates the analog pixel signal. The D/A converter includes a split capacitor, first capacitors, second capacitors, a switch array, a third capacitor, and a multiplexer. The first capacitors each have a first electrode coupled to the output node. The second capacitors are coupled to a second electrode of the split capacitor. The switch array is coupled to a second electrode of each of the first and second capacitors and is adapted to generate the analog reference signal at the output node by selectively applying a first reference voltage. The third capacitor is coupled to the second electrode of the split capacitor. The multiplexer is coupled to a second electrode of the third capacitor and is adapted to generate the analog reference signal at the output node by selectively applying a second reference voltage.

In some embodiments, a resistor string digital to analog converter (DAC) comprises a first plurality of resistors disposed in a first column. Each of the first plurality of resistors couples to an output of the first column via one of a first plurality of switches. The DAC also comprises a second plurality of resistors disposed in a second column. Each of the second plurality of resistors couples to an output of the second column via one of a second plurality of switches. The second plurality of resistors is configured to couple in series with the first plurality of resistors. A first row selection signal is to control a first switch of the first plurality of switches and a second switch of the second plurality of switches. The first switch corresponds to a first resistor disposed at a top of the first column, and the second switch corresponds to a second resistor disposed at a bottom of the second column.

The present application discloses a low-voltage digital to analog conversion circuit, a data driving circuit and a display system. At least one voltage dividing unit comprises a number of resistors connected in series between a lower limit of voltage and an upper limit of voltage, and voltage dividing output terminals drawn from the resistors' connection nodes and an upper limit of voltage connection end. Introducing the voltage dividing unit renders the low-voltage digital signal to analog signal conversion circuit, the data driving circuit, and the display system low-voltage devices with low power consumption and small chip area.

A circuit device includes a control circuit having a successive approximation register, a D/A conversion circuit adapted to perform D/A conversion on output data from the successive approximation register, and a comparison circuit adapted to compare an analog input signal and an output signal from the D/A conversion circuit with each other, the control circuit includes an upper limit value register and a lower limit value register adapted to respectively hold an upper limit value and a lower limit value of a conversion range, and increases the upper limit value or decreases the lower limit value in the case in which the same comparison result has been output by the comparison circuit a predetermined number of times or more.

A single chip dual-channel driver for two independent traveling wave modulators. The driver includes two differential pairs inputs per channel respectively configured to receive two digital differential pair signals. The driver further includes a two-bit DAC per channel coupled to the two differential pairs inputs to produce a single analog differential pair PAM signal at a differential pair output for driving a traveling wave modulator. Additionally, the driver includes a control block having internal voltage/current signal generators respective coupled to each input and the 2-bit DAC for providing a bias voltage, a tail current, a dither signal to assist modulation control per channel. Furthermore, the driver includes an internal I2C communication block coupled to a high-speed clock generator to generate control signals to the control block and coupled to host via an I2C digital communication interface.

A device includes a resistor string that includes a plurality resistors with voltage taps disposed therebetween. The device may select one particular voltage tap of the plurality of voltage taps based on received gray level data for a pixel of a display. The device also includes a first amplifier that may be coupled to a first terminal end of the resistor string. The device additionally includes a second amplifier that may be coupled to a second terminal end of the resistor string, wherein the plurality of voltage taps may each supply a tap voltage derived from a voltage between the first amplifier and the second amplifier, wherein any tap amplifier of the device coupled to a voltage tap of the plurality of voltage taps provides a reference voltage thereto.

A single chip dual-channel driver for two independent traveling wave modulators. The driver includes two differential pairs inputs per channel respectively configured to receive two digital differential pair signals. The driver further includes a two-bit DAC per channel coupled to the two differential pairs inputs to produce a single analog differential pair PAM signal at a differential pair output for driving a traveling wave modulator. Additionally, the driver includes a control block having internal voltage/current signal generators respective coupled to each input and the 2-bit DAC for providing a bias voltage, a tail current, a dither signal to assist modulation control per channel. Furthermore, the driver includes an internal I2C communication block coupled to a high-speed clock generator to generate control signals to the control block and coupled to host via an I2C digital communication interface.