Clock alignment circuitry may include phase detection circuitry and programmable delay circuitry to facilitate aligning a data signal with a particular state of a clock signal. For example, phase detection circuitry may be disposed at a location of interest to monitor the relative timing of the clock signal and the data signal. Based on the monitored states, the programmable delay circuitry may determine the delay to be applied to the data signal (e.g., prior to propagating through logic operations and transmission to the location of interest) such that the data signal later arrives at the location of interest at a suitable time. Effectively, a programmable delay is added to the delay encountered by the data signal during processing and transmission to the location of interest such that the total delay results in the data signal arriving at the location of interest while the clock signal is in the desired state.

Clock alignment circuitry may include phase detection circuitry and programmable delay circuitry to facilitate aligning a data signal with a particular state of a clock signal. For example, phase detection circuitry may be disposed at a location of interest to monitor the relative timing of the clock signal and the data signal. Based on the monitored states, the programmable delay circuitry may determine the delay to be applied to the data signal (e.g., prior to propagating through logic operations and transmission to the location of interest) such that the data signal later arrives at the location of interest at a suitable time. Effectively, a programmable delay is added to the delay encountered by the data signal during processing and transmission to the location of interest such that the total delay results in the data signal arriving at the location of interest while the clock signal is in the desired state.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

Various embodiments of the present technology may comprise methods and apparatus for a multi-cycle time-based ADC configured to convert an analog signal to a digital value. Methods and apparatus a multi-cycle time-based ADC according to various aspects of the present invention may comprise a plurality of VTCs configured to perform multiple voltage-to-time conversions out-of-phase from each other. The integration times for each VTC may be summed to provide a total integration time, which may then be converted to the digital value.

The systems and methods discussed herein utilized a wireless or wired transceiver having a transmitter and a receiver. The transceiver is configured to reduce distortion contributions associated with echo cancelling. The transmitter provides a replica signal and a transmit signal. The replica signal and the transmit signal can be provided using a common switch.

A digital-analog converter of the disclosure converts digital image data to generate analog data signals. The digital-analog converter includes a voltage divider which generates a plurality of gamma reference voltages based on a first reference voltage and a second reference voltage; a global ramp including a plurality of gamma decoders which generates a plurality of global gamma voltages based on the gamma reference voltages; a decoder which selects one of the global gamma voltages according to the digital image data to generate the analog data signals; and a ramp controller which turns off at least some of the gamma decoders based on the digital image data.

Present invention discloses an ADC and an analog-to-digital conversion method. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

Present invention discloses an ADC and an analog-to-digital conversion method. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

An electronic control unit includes a pair of D/A conversion circuits, which performs D/A conversion processing of a pair of digital data and outputs a pair of analog signals. Each of the pair of D/A conversion circuits performs the D/A conversion processing by splitting input digital data into more-significant digital data and less-significant digital data. More-significant D/A conversion part performs analog conversion processing in accordance with the more-significant digital data by using an element string circuit, which outputs split voltages by splitting predetermined reference voltages. The more-significant conversion circuits output a maximum value and a minimum value in absolute voltage ranges, which are different from each other, in accordance with the more-significant digital data. Less-significant conversion parts perform analog conversion processing in accordance with less-significant digital data by using the maximum value and the minimum value of the different absolute voltage ranges, which are outputted from the more-significant D/A conversion parts, as reference voltages. The element string circuit is shared by the pair of D/A conversion circuits.

An electronic control unit includes a pair of D/A conversion circuits, which performs D/A conversion processing of a pair of digital data and outputs a pair of analog signals. Each of the pair of D/A conversion circuits performs the D/A conversion processing by splitting input digital data into more-significant digital data and less-significant digital data. More-significant D/A conversion part performs analog conversion processing in accordance with the more-significant digital data by using an element string circuit, which outputs split voltages by splitting predetermined reference voltages. The more-significant conversion circuits output a maximum value and a minimum value in absolute voltage ranges, which are different from each other, in accordance with the more-significant digital data. Less-significant conversion parts perform analog conversion processing in accordance with less-significant digital data by using the maximum value and the minimum value of the different absolute voltage ranges, which are outputted from the more-significant D/A conversion parts, as reference voltages. The element string circuit is shared by the pair of D/A conversion circuits.