A quad signal generator circuit generates four 2.sup.N−1 bit control signals in response to a sampling clock and a 2.sup.N−1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2.sup.N−1 unit resistor elements, with each unit resistor element including four switching circuits controlled by corresponding bits of the four 2.sup.N−1 bit control signals. Outputs of the 2.sup.N−1 unit resistor elements are summed to generate an analog output signal. The quad signal generator circuit controls generation of the four 2.sup.N−1 bit control signals such that all logic states of bits of the four 2.sup.N−1 bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2.sup.N−1 bit thermometer coded signal.

A digital-analog conversion circuit includes an arithmetic circuit, a voltage output unit, decoders, and output lines. The arithmetic circuit receives a digital signal of multiple bits, divides the multiple bits into groups of two or more bits, and outputs a logical operation result of each group. The voltage output unit outputs voltages having different values. The decoders receive each voltage and the logical operation result, and outputs an analog signal corresponding to the digital signal. The output lines correspond to the decoders. Each decoder includes switches and selection units. The switches correspond to the voltages. Each switch alternates between output, of a corresponding voltage, to a corresponding output line and non-output, of a corresponding voltage, to a corresponding output line. The selection units correspond to the switches. The selection units receive the logical operation result, and each selection unit controls a corresponding switch based on the logical operation result.

A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a multiplexer coupled to the voltage divider, an operational amplifier that may receive a voltage from the multiplexer, and a plurality of resistors that may receive an output from the operational amplifier. The reference voltages may be provided from output terminals coupled to the resistors. A reference voltage generator may include a voltage divider, two multiplexers coupled to the voltage divider, an operational amplifier coupled to each multiplexer, and a plurality of resistors coupled between the outputs of the two operational amplifiers. Reference voltages may be provided from output terminals coupled to the resistors.

A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a multiplexer coupled to the voltage divider, an operational amplifier that may receive a voltage from the multiplexer, and a plurality of resistors that may receive an output from the operational amplifier. The reference voltages may be provided from output terminals coupled to the resistors. A reference voltage generator may include a voltage divider, two multiplexers coupled to the voltage divider, an operational amplifier coupled to each multiplexer, and a plurality of resistors coupled between the outputs of the two operational amplifiers. Reference voltages may be provided from output terminals coupled to the resistors.

A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.

A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.

The present invention provides a driving circuit for a gamma voltage generator of a source driver. The gamma voltage generator includes a resistor string having a plurality of tap nodes, among which a plurality of first tap nodes are respectively connected to a plurality of first buffers. The driving circuit includes a second buffer, a digital-to-analog converter (DAC) and a control circuit. The second buffer is connected to a second tap node other than the plurality of first tap nodes among the plurality of tap nodes. The DAC is coupled to the second buffer. The control circuit, coupled to the DAC, is configured to receive a plurality of first control signals for the plurality of first buffers and calculate a second control signal for the DAC according to the plurality of first control signals.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal according to a decoded digital signal. Latches may be used at one or more levels of decoding and may be activated according to a clock signal to recapture the at least partially decoded data signals to maintain/improve the synchronicity of activation of the unit cells. However, the latches may consume additional power during operation. As such, clock tracking techniques such as static clock tracking, dynamic clock tracking, or differential clock tracking may be utilized to generate a clock path activation signal that gates the clock signal and determines which latches to ignore (e.g., leave inactive). In this manner, instead of activating each latch for every digital signal, clock tracking may be implemented to deactivate latches that do not provide useful updates to the decoded digital signal received at the unit cells.

A digital-to-analog converter includes: a first partial circuit with a first bank of resistors and a first group of switches; a second partial circuit; a first resistor; a third partial circuit with a third bank of resistors and a third group of switches; and a fourth partial circuit with a fourth bank of resistors and a fourth group of switches Supposing that the first resistor has a resistance value R, the fourth bank of resistors has a combined resistance value of 2.sup.(n-m)R, the first bank of resistors has a combined resistance value of (2.sup.m−1)R, the third bank of resistors has a combined resistance value of (2.sup.m−1)R, and the second partial circuit has a combined resistance value of R/(2.sup.(n-m)−1).