A controlled switch having N inputs and a single output (N2) is switchable between N states. In each state a respective one of the inputs is connected to the single output. There are N sources of sub-streams of analog samples, each sub-stream composed of pairs of adjacent analog samples. Each source is coupled to a respective one of the inputs. In operation, the controlled switch is controlled by a control signal to switch between the N states. While the controlled switch is in any one of the states, a data transition occurs between two adjacent analog samples in the sub-stream whose source is coupled to the input that is connected to the single output. The single output yields a high-bandwidth analog signal. Any pair of adjacent analog samples in any one of the sub-streams substantially determines a corresponding pair of adjacent analog samples in the high-bandwidth analog signal.

A controlled switch having N inputs and a single output (N2) is switchable between N states. In each state a respective one of the inputs is connected to the single output. There are N sources of sub-streams of analog samples, each sub-stream composed of pairs of adjacent analog samples. Each source is coupled to a respective one of the inputs. In operation, the controlled switch is controlled by a control signal to switch between the N states. While the controlled switch is in any one of the states, a data transition occurs between two adjacent analog samples in the sub-stream whose source is coupled to the input that is connected to the single output. The single output yields a high-bandwidth analog signal. Any pair of adjacent analog samples in any one of the sub-streams substantially determines a corresponding pair of adjacent analog samples in the high-bandwidth analog signal.

A novel semiconductor device with high convenience or high reliability is provided. The semiconductor device includes an arithmetic logic unit and an amplifier. The arithmetic logic unit is configured to generate second data on the basis of an offset adjustment signal or offset data and first data. The amplifier includes an operational amplifier and an offset adjustment circuit including a register. The operational amplifier supplies a predetermined voltage to a node on the basis of a voltage between a first terminal and a second terminal. The register is configured to retain, as the offset data, the offset adjustment signal on the basis of a latch signal. The register is configured to allow the supplied offset adjustment signal to pass therethrough in a passage state and supply the offset adjustment signal. The register is configured to supply the offset data in a non-passage state.

Embodiments of the present disclosure provide a digital-to-analog converter, a conversion circuit and a display device. An M-bit digital-to-analog converter includes a higher MN-bit digital-to-analog conversion circuit, a voltage conversion circuit, an output circuit. The higher MN-bit digital-to-analog conversion circuit includes: a higher MN-bit voltage division generation circuit, a first voltage selection circuit. The first voltage selection circuit selects a first voltage from the higher MN-bit voltage division generation circuit based on a higher MN-bit digital signal, to be output from a first voltage end. The voltage conversion circuit charges a capacitor circuit under the control of a first switch circuit and a second switch circuit, and discharges a second voltage to a second voltage end through the capacitor circuit. The output circuit controls the first voltage and the second voltage based on a lower N-bit digital signal, generates an analog voltage signal corresponding to an M-bit digital signal.

Embodiments of the present disclosure provide a digital-to-analog converter, a conversion circuit and a display device. An M-bit digital-to-analog converter includes a higher MN-bit digital-to-analog conversion circuit, a voltage conversion circuit, an output circuit. The higher MN-bit digital-to-analog conversion circuit includes: a higher MN-bit voltage division generation circuit, a first voltage selection circuit. The first voltage selection circuit selects a first voltage from the higher MN-bit voltage division generation circuit based on a higher MN-bit digital signal, to be output from a first voltage end. The voltage conversion circuit charges a capacitor circuit under the control of a first switch circuit and a second switch circuit, and discharges a second voltage to a second voltage end through the capacitor circuit. The output circuit controls the first voltage and the second voltage based on a lower N-bit digital signal, generates an analog voltage signal corresponding to an M-bit digital signal.

A digital-analog conversion circuit includes an arithmetic circuit, a voltage output unit, decoders, and output lines. The arithmetic circuit receives a digital signal of multiple bits, divides the multiple bits into groups of two or more bits, and outputs a logical operation result of each group. The voltage output unit outputs voltages having different values. The decoders receive each voltage and the logical operation result, and outputs an analog signal corresponding to the digital signal. The output lines correspond to the decoders. Each decoder includes switches and selection units. The switches correspond to the voltages. Each switch alternates between output, of a corresponding voltage, to a corresponding output line and non-output, of a corresponding voltage, to a corresponding output line. The selection units correspond to the switches. The selection units receive the logical operation result, and each selection unit controls a corresponding switch based on the logical operation result.

Techniques are described that can be used to extract an offset and a gain of a signal chain, which can be used for digital correction of an analog-to-digital converter (ADC) output to help achieve a life time and temperature stable ADC output. For example, using various techniques, a value for a voltage reference VREF and a value for ground (GND) (or other reference voltage) can be converted, which can then be used to determine gain and offset, respectively, of the signal chain.

Techniques are described that can be used to extract an offset and a gain of a signal chain, which can be used for digital correction of an analog-to-digital converter (ADC) output to help achieve a life time and temperature stable ADC output. For example, using various techniques, a value for a voltage reference VREF and a value for ground (GND) (or other reference voltage) can be converted, which can then be used to determine gain and offset, respectively, of the signal chain.

The present invention provides a driving circuit for a gamma voltage generator of a source driver. The gamma voltage generator includes a resistor string having a plurality of tap nodes, among which a plurality of first tap nodes are respectively connected to a plurality of first buffers. The driving circuit includes a second buffer, a digital-to-analog converter (DAC) and a control circuit. The second buffer is connected to a second tap node other than the plurality of first tap nodes among the plurality of tap nodes. The DAC is coupled to the second buffer. The control circuit, coupled to the DAC, is configured to receive a plurality of first control signals for the plurality of first buffers and calculate a second control signal for the DAC according to the plurality of first control signals.

A digital-to-analog converter (DAC) capable of operating in radio frequency (RF) with linear output, low distortion, low power consumption, and input data independence. The DAC includes switch drivers and output switches driven by the switch drivers. The switch drivers include pairs of outputs, and positive feedback circuitries coupled between respective pairs of outputs. The output switches are arranged between a first current source configured to push current to the DAC's outputs and a second current source configured to pull current from the DAC's outputs. Different output switches are configured to push current to and pull current from the DAC's outputs in accordance with rising edges and falling edges, respectively.