A digital-to-analog converter includes a resistor ladder, a first switch and a protection circuit. The first switch includes a first terminal and a second terminal that are respectively coupled to a rung of the resistor ladder and a reference voltage node. The protection circuit is coupled to the reference voltage node and to a reference voltage input terminal. The protection circuit includes a second switch, a third switch, and a fourth switch. First and second terminals of the second switch are respectively coupled to the reference voltage node and the reference voltage input terminal. First and second terminals of the third switch are respectively coupled to the reference voltage node and a reference voltage feedback terminal. The first and second terminals of the fourth switch are respectively coupled to the reference voltage input terminal and the reference voltage feedback terminal.

A DAC (60) is disclosed. It comprises an input port comprising N input terminals p.sub.1, p.sub.2, . . . , p.sub.N configured to receive voltages representing N input bits b.sub.1, b.sub.2, . . . , b.sub.N, respectively, wherein the significance of b.sub.j is higher than for b.sub.j1 for j=2, 3, . . . , N. Furthermore, it comprises a capacitor ladder circuit (100) comprising N capacitors C.sub.1, C.sub.2, . . . , C.sub.N with capacitance C, each having a first terminal and a second terminal. Capacitor C.sub.j is connected with its first terminal to the terminal p.sub.j of the input port. For each j=1, 2, . . . , N1, the capacitor ladder circuit (100) comprises a capacitor (150.sub.j) with capacitance xC connected between the second terminal of capacitor C.sub.j and the second terminal of capacitor C.sub.j+1. The DAC (60) also comprises an input circuit (140) connected to the input port comprising at least one capacitor (160.sub.1-160.sub.N), each connected between a unique one of the input terminals p.sub.1, p.sub.2, . . . , p.sub.N of the input port and signal ground.

A DAC (60) is disclosed. It comprises an input port comprising N input terminals p.sub.1, p.sub.2, . . . , p.sub.N configured to receive voltages representing N input bits b.sub.1, b.sub.2, . . . , b.sub.N, respectively, wherein the significance of b.sub.j is higher than for b.sub.j1 for j=2, 3, . . . , N. Furthermore, it comprises a capacitor ladder circuit (100) comprising N capacitors C.sub.1, C.sub.2, . . . , C.sub.N with capacitance C, each having a first terminal and a second terminal. Capacitor C.sub.j is connected with its first terminal to the terminal p.sub.j of the input port. For each j=1, 2, . . . , N1, the capacitor ladder circuit (100) comprises a capacitor (150.sub.j) with capacitance xC connected between the second terminal of capacitor C.sub.j and the second terminal of capacitor C.sub.j+1. The DAC (60) also comprises an input circuit (140) connected to the input port comprising at least one capacitor (160.sub.1-160.sub.N), each connected between a unique one of the input terminals p.sub.1, p.sub.2, . . . , p.sub.N of the input port and signal ground.

A sensor arrangement comprises a sensor having a first terminal and a second terminal, and an amplifier having an amplifier input for applying an input signal and an amplifier output for providing an amplified input signal, the amplifier input being coupled to the second terminal. The sensor arrangement further comprises a quantizer having a quantizer input and a quantizer output being suitable for providing a multi-level output signal on the basis of the amplified input signal and a feedback circuit having a feedback circuit input coupled to the quantizer output and a feedback circuit output coupled to the first terminal. The feedback circuit comprises a digital-to-analog converter being suitable for generating an analog signal on the basis of the multi-level output signal, the analog signal being the basis of a feedback signal provided at the feedback circuit output. The feedback circuit further comprises a feedback capacitor that is coupled between the feedback circuit output and an output of the digital-to-analog converter, and a voltage source coupled to the feedback circuit output.

A device for monitoring voltage in a battery-operated system, the device comprising: a ladder selector configured to select between a first resistive ladder and a second resistive ladder; the first resistive ladder comprising: a first string of resistors coupled between a sensing input node and a first node of the ladder selector; and a first set of transistors configured to tap intermediate nodes of a set of resistors in the first string of resistors; the second resistive ladder comprising: a second string of resistors coupled between the sensing input node and a second node of the ladder selector; and a second set of transistors configured to tap intermediate nodes of a set of resistors in the second string of resistors; and wherein a selected transistor in one of the first set of transistors or the second set of transistors is turned on, and non-selected transistors of the first set of transistors and the second set of transistors are turned off to set a threshold voltage for a sensing output node.

A digital to analog converter, a method for driving the same, and a display device are provided. The digital to analog converter includes: a first resistor string, 2.sup.m first multiplexers, a first voltage selector, a second resistor string, a second voltage selector, and a second multiplexer, where the 2.sup.m first multiplexers, the first voltage selector, and the second voltage selector operate in cooperation with each other so that the entire second resistor string can be connected in series to the first resistor string for further division.

A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.

A digital to analog converter (DAC) that receives a binary coded signal and generates an analog output signal includes a binary-to-thermometer decoder and a resistive network. The decoder receives the binary coded signal, and decodes it into thermometer signals. The resistive network has branches that are coupled to an output terminal of the DAC in response to the thermometer signals. Each of the branches includes first and second resistors, and a switch. The first resistor is coupled between a first reference voltage and the switch, and the second resistor is coupled between a second reference voltage and the switch. The switch couples either the first resistor or the second resistor to the output terminal in response to a corresponding thermometer signal.

A digital to analog converter (DAC) that receives a binary coded signal and generates an analog output signal includes a binary-to-thermometer decoder and a resistive network. The decoder receives the binary coded signal, and decodes it into thermometer signals. The resistive network has branches that are coupled to an output terminal of the DAC in response to the thermometer signals. Each of the branches includes first and second resistors, and a switch. The first resistor is coupled between a first reference voltage and the switch, and the second resistor is coupled between a second reference voltage and the switch. The switch couples either the first resistor or the second resistor to the output terminal in response to a corresponding thermometer signal.

High efficiency amplitude DACs (Digital-to-Analog Converters) and RFDACs (Radio Frequency DACs) employing such amplitude DACs are discussed. One exemplary embodiment is a DAC comprising a plurality of DAC stages, wherein each DAC stage of the plurality of DAC stages is associated with a respective predetermined voltage of a plurality of predetermined voltages, wherein each DAC stage of the plurality of DAC stages can receive a digital signal at the respective predetermined voltage associated with that DAC stage when the respective predetermined voltage of that DAC stage is a selected predetermined voltage, wherein the selected predetermined voltage is based on an amplitude of the digital signal, and wherein each DAC stage of the plurality of DAC stages can generate a respective analog signal associated with that DAC stage based on the digital signal received at that DAC stage when the respective predetermined voltage of that DAC stage is the selected predetermined voltage.